Abstract: A method and apparatus for integrating a plurality of analog input signals. A first integrator(725) having a first pole frequency integrates a first of the input signals and a second integrator(730) having a second pole frequency different than the first pole frequency integrates a second of the input signals. A summer(735) is connected to the first and second integrators to then sum the integrated first and second signals and provide a composite integrated signal prior to transmitting a communications signal.

Abstract: An interference dependent adaptive phase clock controller method and system includes synthesis of a signal processing clock signal (307). An interference signal (311 ) dependent on a phase of the signal processing clock signal is measured, and a phase correction signal (317) is provided dependent thereon. A magnitude of the interference signal is reduced by adjusting the phase of the signal processing clock signal (307) dependent on the phase correction signal (317).

Abstract: A low voltage differential amplifier 10 or comparator is accomplished by providing an differential amplifier 10 that includes a transistor bias simulator 32 and a capacitance circuit 36. The transistor bias simulator 32 matches the gate to source bias voltage of the load transistor 22 and provides this value to the capacitance circuit 36. The capacitance circuit 36, which is coupled to a biasing reference voltage 38, charges a capacitor 84 based on the difference between the biasing reference voltage 38 and the simulated bias voltage 34. This charged capacitor 86 is used during an auto-zeroing phase to bias the drain to source voltage of the load transistor 22 to a state at which it is just beyond the onset of saturation.

Abstract: A diagnostic system for measuring behavior of signals provided by a plurality of sensors (101, 129) includes a plurality of input filters (107, 135) for receiving signals (105, 133) from each of the plurality of sensors (103, 131) and for providing a plurality of filtered sensor signals (109, 137) each derived from the received signals (105, 133). A signal bandwidth of each of the plurality of filtered sensor signals (109, 137) is lower than a signal bandwidth of the than a signal bandwidth of the associated received signal. A selection circuit (119) receives each of the signals (105, 133) from each of the plurality of sensors (103, 131) and, dependent on a selection signal (127), provides a selected sensor signal (121) derived from one of the received signals (105), wherein the selected sensor signal (121) has a signal bandwidth greater than one of the filtered sensor signals (109) derived from the one of the received signals (105).

Abstract: An apparatus and a method for minimizing the turn on time for a receiver operating in a discontinuous receive mode. In a communication unit the receiver receives a signal (118) having desirable data (word A) and undesirable data (word B). The receiver (104) has a discontinuous receive mode of operation wherein the receiver (104) is turned on when expecting the desirable data (word A) and turned off when expecting the undesirable data (word B). A duration of time that the receiver (104) has been turned off is determined. The receiver (104) is turned on at time prior to the arrival of the desirable data (word A) responsive to the duration of time that the receiver (104) has been turned off. The present invention advantageously minimizes the turn on time for the receiver (104) operating in a discontinuous receive mode to save current drain.

Abstract: A low-voltage differential amplifier (10) includes a circuit (12) having a differential pair (14) and loads (22 and 24). The first load (22) can include a first embedded differential amplifier (30) and an output transistor (32) and the second load (24) can include a second embedded differential amplifier (36) and an output transistor (38). The differential amplifier (10) can provide a wide-voltage operable range. The differential amplifier (10) is particularly useful in connection with low-voltage temperature compensated crystal oscillators.

Abstract: A buffer (200) having output devices (101 and 102) exhibiting complementary symmetry and configured as voltage-followers in push pull is biased for class AB operation by a bias network including two substantially equal resistors (201 and 202) arranged and configured to substantially reduce noise attributable to the bias circuit.

Abstract: What is described is a high efficiency voltage doubler (100). The high efficiency voltage doubler (100), has a charge-pump capacitor (30), an inverter (18), a coupling capacitor (24), a complementary switch pair (16), a DC biasing circuit (102), a charging circuit (106), and an input circuit (108). This structure is adapted for use in an integrated circuit, and provides the advantage of maximizing voltage doubled power output and minimizing current consumption with a minimal number of components.

Abstract: A temperature compensated crystal oscillator (10), has a crystal oscillator circuit (12), a voltage controlled reactance element (30), a temperature compensation network (50), and a programmable DC-DC converter network (60) having an output (62) connected to the voltage controlled reactance element (30), or the temperature compensation network (50) or both. The DC-DC converter network (60) provides the capability of operating over an extended voltage range, by increasing the supply voltage to a level necessary to operate the voltage controlled reactance element (30). Much of this structure is adapted for use in an integrated circuit, and provides the advantages of minimizing power and current consumption.

Abstract: An improved auto-zeroing feedback control circuit (FIG. 1) is disclosed to compensate for DC offset voltages in signal coding applications. The feedback control circuit for a signal limiter (120) includes a digital integrator (130) which oversamples the limited output (125). When the accumulated sample count overflows, an analog integrator (140) is enabled, and a small quantity of charge is delivered to the integrating capacitor. The analog integrator output signal (145) is then attenuated (150) and used to adjust the bias for the limiter (120). This improved auto-zeroing technique eliminates the requirement of a large external auto-zero capacitor, and permits the signal coder to be fully integrated on-chip.

Abstract: A low current CMOS translator arrangement is disclosed that utilizes a low current inverting stage, having a peak current requirement, fed by a constant current source at a supply node that also has a capacitor coupled to it. This low current inverter is useful for a number of applications, including generating a sinusoidal signal when it is coupled to a crystal. When one or more are cascaded and coupled to a square wave input signal, the arrangement becomes a low current translator that level-shifts, or translates, the input signal having a first voltage range to a translated square wave output signal having a second voltage range. In another embodiment called a low current squaring translator, a squaring stage is coupled between the low current inverter and a low current translator that includes one or more inverting stages. This arrangement is able to achieve an output signal that maintains a precise duty cycle with low noise at a very low current.

Abstract: A fully integrated, adjustable oscillator circuit for use with a crystal is disclosed in which a crystal oscillator, such as a Pierce oscillator, is arranged to utilize a tuning network that includes at least one integrated varactor (voltage-variable-capacitor) as a shunt element for providing at least one type of adjustment of the oscillating signal. More than one type of adjustment can be provided by including a bank of varactors for each of the shunt elements of the tuning network, in which various individual varactors are selected in binary (on-off) fashion to effect digital as well as analog adjustment of the crystal oscillator.

Abstract: A differential input circuit for a switched capacitor CMOS voltage comparator is provided which minimizes offset voltages by configuring the load devices to utilize a single switched capacitor biasing network initialized from internally-generated bias voltages, while configuring the initialization switches for the differential input devices to also utilize internally-generated bias voltages such that the offset voltages are stored on the input capacitors. The power supply rejection performance of the voltage comparator is also optimized by connecting parallel load devices of opposite switching topology such that the same input impedance is seen at both load terminals.

Abstract: A unique interface adapter is coupled to a microprocessor by a three-wire self-clocking serial data bus for accommodating a twenty-key keyboard and an eight-digit display. The interface adapter includes circuitry for recovering a clock signal and a non-return-to-zero (NRZ) data signal from the data signal transmitted on two forward signal lines of the serial data bus. The NRZ data signal is shifted into a receiving register, where address circuitry decodes the address portion of the data signal to provide a chip select signal and control circuitry decodes the control portion of the data signal to provide a register select signal, read/write signal and bus sense signal. The register select signal determines whether a control register or display register is to be loaded in response to the read/write signal with the data portion of the data signal.