Patents by Inventor Lawrence E. Connell
Lawrence E. Connell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140361821Abstract: An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a first clock switch configured to couple the differential inverter to a voltage source, a second clock switch configured to couple the differential inverter to a ground, wherein the first clock switch and the second clock switch are configured to receive a differential clock signal, and wherein the first clock switch and the second clock switch are both open or both closed depending on the differential clock signal, a second latch, wherein the first latch and the second latch are configured as a frequency divider, and a logic circuit coupled to each latch, wherein the logic circuits are configured to generate both an in-phase reference output signal and a quadrature output signal.Type: ApplicationFiled: July 3, 2013Publication date: December 11, 2014Inventors: Lawrence E. Connell, Daniel P. McCarthy, Brian T. Creed, Kent Jaeger
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Patent number: 8676145Abstract: A balanced mixer circuit (300, 400, 500, 600, 700 and 800) in a baseband receiver (202) includes an oscillator circuit (212), a mixer (214 and 215), a digital-to-analog converter (258 and 259) and a digital signal processor (250). The mixer includes CMOS devices (301, 302, 303 and 304). In response to differential outputs from the mixer, the digital signal processor controls the digital-to-analog converter to output bias voltages for the gate of at least one of the CMOS devices of the mixer to compensate for imbalance in the differential output of the mixer that may be caused by mismatch among two or more CMOS devices of the mixer or caused by other reasons, in order to increase second order intercept point of the mixer.Type: GrantFiled: April 27, 2011Date of Patent: March 18, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Daniel L. Kaczman, Lawrence E. Connell, Joseph P. Golat, Manish N. Shah
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Patent number: 8588726Abstract: An apparatus comprising a low noise mixer comprising a transconductance amplifier configured to receive a differential voltage and to generate a differential current signal, a passive mixer directly connected to an output of the transconductance amplifier, and a transimpedance amplifier coupled to the passive mixer, wherein the transimpedance amplifier is configured to receive a current signal and convert the current signal to a voltage signal.Type: GrantFiled: January 30, 2012Date of Patent: November 19, 2013Assignee: Futurewei Technologies, Inc.Inventors: Lawrence E. Connell, Daniel P. McCarthy
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Publication number: 20120200334Abstract: An apparatus comprising a low noise mixer comprising a transconductance amplifier configured to receive a differential voltage and to generate a differential current signal, a passive mixer directly connected to an output of the transconductance amplifier, and a transimpedance amplifier coupled to the passive mixer, wherein the transimpedance amplifier is configured to receive a current signal and convert the current signal to a voltage signal.Type: ApplicationFiled: January 30, 2012Publication date: August 9, 2012Applicant: FUTUREWEI TECHNOLOGIES, INC.Inventors: Lawrence E. Connell, Daniel P. McCarthy
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Patent number: 8131241Abstract: A variable attenuator and method of attenuating a signal is presented. The variable attenuator contains an input that receives an input signal to be attenuated. A voltage divider between a resistor and parallel MOSFETs provides the attenuated input signal. The MOSFETs have different sizes and have gates that are connected to a control signal through different resistances such that the larger the MOSFET, the larger the resistance. The control signal is dependent on the output of the attenuator. The arrangement extends the linearity of the attenuation over a wide voltage range of the control signal and decreases the intermodulation distortion of the attenuator.Type: GrantFiled: February 5, 2009Date of Patent: March 6, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Daniel P. McCarthy, Lawrence E. Connell, Neal W. Hollenbeck
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Patent number: 8126422Abstract: A receiver (300) comprises an antenna input (301), a filter (302), a voltage-to-current converter (303), a down frequency conversion mixer (304), and a current-to-voltage converter (305). The antenna input operably couples to an antenna. The filter has a filter input that operably couples to the antenna input and can further have a filter output. The voltage-to-current converter has an input that is operably coupled to the filter output and can further have a voltage-to-current converter output. The down frequency conversion mixer has a mixer input that is operably coupled to the voltage-to-current converter output and can further have a mixer output. And the current-to-voltage converter has an input that is operably coupled to the mixer output and can further have a current-to-voltage converter output. By one approach, this current-to-voltage converter comprises an amplifier having a current gain of substantially unity or less.Type: GrantFiled: April 15, 2008Date of Patent: February 28, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Lawrence E. Connell, Joseph P. Golat, Joseph M. Ingino
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Patent number: 8010074Abstract: A balanced mixer circuit (300, 400, 500, 600, 700 and 800) in a baseband receiver (202) includes an oscillator circuit (212), a mixer (214 and 215), a digital-to-analog converter (258 and 259) and a digital signal processor (250). The mixer includes CMOS devices (301, 302, 303 and 304). In response to differential outputs from the mixer, the digital signal processor controls the digital-to-analog converter to output bias voltages for the gate of at least one of the CMOS devices of the mixer to compensate for imbalance in the differential output of the mixer that may be caused by mismatch among two or more CMOS devices of the mixer or caused by other reasons, in order to increase second order intercept point of the mixer.Type: GrantFiled: February 8, 2008Date of Patent: August 30, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Daniel L. Kaczman, Lawrence E. Connell, Joseph P. Golat, Manish N. Shah
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Publication number: 20110201296Abstract: A balanced mixer circuit (300, 400, 500, 600, 700 and 800) in a baseband receiver (202) includes an oscillator circuit (212), a mixer (214 and 215), a digital-to-analog converter (258 and 259) and a digital signal processor (250). The mixer includes CMOS devices (301, 302, 303 and 304). In response to differential outputs from the mixer, the digital signal processor controls the digital-to-analog converter to output bias voltages for the gate of at least one of the CMOS devices of the mixer to compensate for imbalance in the differential output of the mixer that may be caused by mismatch among two or more CMOS devices of the mixer or caused by other reasons, in order to increase second order intercept point of the mixer.Type: ApplicationFiled: April 27, 2011Publication date: August 18, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Daniel L. KACZMAN, Manish N. SHAH, Joseph P. GOLAT, Lawrence E. CONNELL
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Patent number: 7751792Abstract: Transmission of a high frequency signal is provided by a passive mixer. The passive mixer receives a low frequency signal as an input. The passive mixer includes a plurality of transistors each with a gate, a source, and a drain. The passive mixer also includes a local oscillator connected to the gates of the transistors. The gates of the transistors are also connected to a DC bias proportional to the threshold voltage of the transistors. In addition, an output of the passive mixer may be attenuated by a passive attenuator wherein both the passive attenuator and passive mixer are substantially free of quiescent current.Type: GrantFiled: March 22, 2005Date of Patent: July 6, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Lawrence E. Connell, David P. Kovac, Poojan A. Wagh, Vikram B. Karnani, William T. Waldie, Tao Wu
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Patent number: 7733181Abstract: Methods and corresponding systems for amplifying an input signal include inputting first and second differential input signals into first and second circuit legs, respectively, wherein the first circuit leg includes a first transistor coupled in series with a first variable current source, and wherein the second circuit leg includes a second transistor coupled in series with a second variable current source. The first and second variable current sources are dynamically set to provide first and second bias currents in response to the first and second differential input signals, wherein the first bias current is set inversely proportional to the second bias current. The first and second bias currents are sunk in the first and second circuit legs, respectively. First and second differential output signals are output from the first and second circuit legs, respectively.Type: GrantFiled: May 23, 2008Date of Patent: June 8, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Kent Jaeger, Lawrence E. Connell
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Publication number: 20090289716Abstract: Methods and corresponding systems for amplifying an input signal include inputting first and second differential input signals into first and second circuit legs, respectively, wherein the first circuit leg includes a first transistor coupled in series with a first variable current source, and wherein the second circuit leg includes a second transistor coupled in series with a second variable current source. The first and second variable current sources are dynamically set to provide first and second bias currents in response to the first and second differential input signals, wherein the first bias current is set inversely proportional to the second bias current. The first and second bias currents are sunk in the first and second circuit legs, respectively. First and second differential output signals are output from the first and second circuit legs, respectively.Type: ApplicationFiled: May 23, 2008Publication date: November 26, 2009Inventors: Kent Jaeger, Lawrence E. Connell
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Patent number: 7609779Abstract: An RF modulator supporting wide-band signals includes IQ modulation by interleaving the in-phase and quadrature signals. The modulator can be implemented using an integrated circuit having a baseband in-phase stage that receives an in-phase analog input signal, a baseband quadrature stage that receives a quadrature analog input signal, and a switching mixer having a plurality of switches. The switching mixer receives in-phase and quadrature signals from the baseband in-phase stage and the baseband quadrature stage. The switching mixer produces a differential signal combining the in-phase and quadrature signals by interleaving the signals over a plurality of phases of a carrier period.Type: GrantFiled: February 27, 2006Date of Patent: October 27, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Poojan A. Wagh, Lawrence E. Connell, Matthew R. Miller
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Publication number: 20090258623Abstract: A receiver (300) comprises an antenna input (301), a filter (302), a voltage-to-current converter (303), a down frequency conversion mixer (304), and a current-to-voltage converter (305). The antenna input operably couples to an antenna. The filter has a filter input that operably couples to the antenna input and can further have a filter output. The voltage-to-current converter has an input that is operably coupled to the filter output and can further have a voltage-to-current converter output. The down frequency conversion mixer has a mixer input that is operably coupled to the voltage-to-current converter output and can further have a mixer output. And the current-to-voltage converter has an input that is operably coupled to the mixer output and can further have a current-to-voltage converter output. By one approach, this current-to-voltage converter comprises an amplifier having a current gain of substantially unity or less.Type: ApplicationFiled: April 15, 2008Publication date: October 15, 2009Inventors: LAWRENCE E. CONNELL, Joseph P. Golat, Joseph M. Ingino
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Patent number: 7583945Abstract: An amplifier and method of amplifying a signal is presented. The amplifier contains a fixed gain stage, a digitally controllable gain stage, and a continuously variable attenuator connected between the fixed and controllable gain stages. The attenuator and controllable gain stage are controllable such that the gain of the controllable gain stage is decreased when the attenuation of the attenuator reaches a predetermined maximum value and the attenuation of the attenuator is reduced thereafter. The output power level of the amplifier remains constant.Type: GrantFiled: January 10, 2006Date of Patent: September 1, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Daniel P. McCarthy, Lawrence E. Connell
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Publication number: 20090203347Abstract: A balanced mixer circuit (300, 400, 500, 600, 700 and 800) in a baseband receiver (202) includes an oscillator circuit (212), a mixer (214 and 215), a digital-to-analog converter (258 and 259) and a digital signal processor (250). The mixer includes CMOS devices (301, 302, 303 and 304). In response to differential outputs from the mixer, the digital signal processor controls the digital-to-analog converter to output bias voltages for the gate of at least one of the CMOS devices of the mixer to compensate for imbalance in the differential output of the mixer that may be caused by mismatch among two or more CMOS devices of the mixer or caused by other reasons, in order to increase second order intercept point of the mixer.Type: ApplicationFiled: February 8, 2008Publication date: August 13, 2009Applicant: Freescale Semiconductor, Inc.Inventors: DANIEL L. KACZMAN, Manish N. Shah, Joseph P. Golat, Lawrence E. Connell
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Publication number: 20090143036Abstract: A variable attenuator and method of attenuating a signal is presented. The variable attenuator contains an input that receives an input signal to be attenuated. A voltage divider between a resistor and parallel MOSFETs provides the attenuated input signal. The MOSFETs have different sizes and have gates that are connected to a control signal through different resistances such that the larger the MOSFET, the larger the resistance. The control signal is dependent on the output of the attenuator. The arrangement extends the linearity of the attenuation over a wide voltage range of the control signal and decreases the intermodulation distortion of the attenuator.Type: ApplicationFiled: February 5, 2009Publication date: June 4, 2009Inventors: Daniel P. McCarthy, Lawrence E. Connell, Neal W. Hollenbeck
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Patent number: 7505748Abstract: A variable attenuator and method of attenuating a signal is presented. The variable attenuator contains an input that receives an input signal to be attenuated. A voltage divider between a resistor and parallel MOSFETs provides the attenuated input signal. The MOSFETs have different sizes and have gates that are connected to a control signal through different resistances such that the larger the MOSFET, the larger the resistance. The control signal is dependent on the output of the attenuator. The arrangement extends the linearity of the attenuation over a wide voltage range of the control signal and decreases the intermodulation distortion of the attenuator.Type: GrantFiled: September 28, 2005Date of Patent: March 17, 2009Assignee: Freescale Semicondductor, Inc.Inventors: Daniel P. McCarthy, Lawrence E. Connell, Neal W. Hollenbeck
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Publication number: 20090051441Abstract: Methods and corresponding systems in a low noise amplifier include selecting a selected sub-band for amplifying, wherein the selected sub-band is one of a plurality of sub-bands, wherein each sub-band is a portion of a frequency band, and wherein each sub-band has a corresponding sub-band center frequency. Next, a gate-source capacitor is adjusted so that a real part of an LNA input impedance corresponds to a real part of a source impedance at the selected sub-band center frequency. A match capacitor is also adjusted so that the LNA input impedance corresponds to the complex conjugate of the source impedance at the selected sub-band center frequency. The gate-source capacitor and the match capacitor can each be adjusted by recalling capacitor values from memory that correspond to the selected sub-band, and connecting selected capacitor components in response to the recalled capacitor values.Type: ApplicationFiled: August 24, 2007Publication date: February 26, 2009Inventors: Jason H. Branch, Lawrence E. Connell, Patrick L. Rakers, Poojan A Wagh
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Patent number: 7495515Abstract: Methods and corresponding systems in a low noise amplifier include selecting a selected sub-band for amplifying, wherein the selected sub-band is one of a plurality of sub-bands, wherein each sub-band is a portion of a frequency band, and wherein each sub-band has a corresponding sub-band center frequency. Next, a gate-source capacitor is adjusted so that a real part of an LNA input impedance corresponds to a real part of a source impedance at the selected sub-band center frequency. A match capacitor is also adjusted so that the LNA input impedance corresponds to the complex conjugate of the source impedance at the selected sub-band center frequency. The gate-source capacitor and the match capacitor can each be adjusted by recalling capacitor values from memory that correspond to the selected sub-band, and connecting selected capacitor components in response to the recalled capacitor values.Type: GrantFiled: August 24, 2007Date of Patent: February 24, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Jason H. Branch, Lawrence E. Connell, Patrick L. Rakers, Poojan A. Wagh
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Patent number: 7403071Abstract: An amplifier, tuner, and method of amplification are provided. The amplifier has a pair of transistors. Each transistor has a control terminal and an output terminal disposed between the transistor and a power supply input. A first network is connected between each power supply input and output terminal. The first network contains a first resistor and a first switch connected in parallel with the first resistor. A second network is connected between the transistors. The second network contains a first and second combination. Each of the first and second combinations contains a second resistor and a second switch connected in parallel with the second resistor. The first and second combinations are connected by a third switch.Type: GrantFiled: March 14, 2006Date of Patent: July 22, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Neal W. Hollenbeck, Lawrence E. Connell, Daniel P. McCarthy