Abstract: A frequency source having a fast start-up time and low noise in steady state is presented. The frequency source includes an oscillator and a hybrid automatic gain control (AGC) loop that switches between an analog AGC loop at oscillator start up and a digital AGC loop at steady state operation. The analog AGC loop includes a peak detector connected to the oscillator and an error integrator integrating the difference between the peak detector output and a reference voltage. The digital AGC loop includes a comparator comparing the peak detector output and high/low reference voltages, an oscillator counter providing a timer signal, a digital-to-analog converter (DAC) supplied with a digital word, and a low pass filter between the DAC and the oscillator. The timer signal causes a multiplexer to select either the analog AGC loop or the digital AGC loop.

Abstract: A closed loop audio amplifier system and method of powering up/down the system without producing audible artifacts are provided. During power up, a prebias voltage is provided to each output connected to a speaker to increase the voltage to a nominal output level. High impedance switches are then driven at a 50% duty cycle. Feedback from the output is supplied to a servo, which is enabled to fine tune the output voltage. Low impedance switches are then driven at a 50% duty cycle at a quarter cycle timing. The order of the feedback loop depends on which of the high or low impedance switches are driven. The prebias voltage is then removed before audio signals to be amplified are supplied to the system. Timing of driving of the switches is programmable. To power down, essentially the reverse sequence is provided.

Abstract: Method and apparatus are provided for high linearity and low noise communication signal mixing. The apparatus includes a high linearity low noise mixer having an input stage coupled to a switch stage by a series-coupled blocking capacitance and input resistance. The input stage includes a buffer with negative feedback, and the switch stage includes a transistor based switch network connected to an amplifier that has feedback resistance and shunting capacitance. The method includes AC coupling an RF signal, increasing a gain of the RF signal, reducing third-order distortion by negatively feeding-back the RF signal, blocking IM2 generated from said gain increasing step, increasing a second-order input intercept point (IIP2) by attenuating the RF signal across a resistance, and applying a local oscillator input to the RF signal.

Abstract: A frequency synthesizer 100 comprising a charge pump 102, a loop filter 104, a loop divider 106, and an active and dual port VCO 110. An integrator 108 low pass filters a steering voltage to provide a low frequency path while the steering voltage provides a high frequency path. Both steering paths are connected to dual port VCO 110. The dual port VCO 110 is a single frequency generator which is controlled by two control signals. The dual port VCO 110, effectively provides the equivalent of a low frequency path 114 and a high frequency noise compensation path 112, both paths effectively merging 116 by superposition.

Abstract: A multiphase voltage controlled oscillator (e.g., a quadrature VCO) 100, which includes multiple voltage controllable transconductance phase drivers 102, 104, 106 and 108. The output of each voltage controllable transconductance phase driver 102, 104, 106, 108 supplies one of 4 oscillator phases and receives 2 of the 4 phases as inputs. Each of the voltage controllable transconductance phase drivers 102, 104, 106 and 108 corresponds to a pair of controllable transconductance inverting amplifiers 132, 134, 136, 138. The controllable transconductance inverting amplifiers may be a simple inverter 150 that includes N-type FET (NFET) 152 and P-type FET (PFET) 154. Transconductance is controlled in the simple inverter by raising or lowering supply voltage (Vdd) levels. A more complex controllable transconductance inverting amplifier may be used, replacing PFET 154 with series connected PFETs 164, 166. The gate of one PFET 166 is controlled by a bias control voltage VCON.

Abstract: A high gain wide-band width RF amplifier 120 with automatic bias supply regulation. The load supply is actively adjusted in response to the amplifier's output signal level. At small output signals effective load supply voltage is minimum and at larger output signals the effective load supply voltages is maximized. The amplifier 120 includes a differential pair of field effect transistors (FETs) 102, 104 connected at common source connection 106 and biased by current bias FET 108 which is connected between common source connection 106 and amplifier signal input RFIN. A bias voltage (VB1) is applied to the gate of bias device 108 and an automatic gain control voltage (VAGC) is applied to the gates of differential FET pair 102, 104. The automatic bias supply circuit 122 is an active load and includes resistors 124, 126, capacitor 128 and a differential amplifier 130. Capacitor 128 is connected between the negative input 132 and the output 134 of differential amplifier 130.

Abstract: A psuedo third order dual steered frequency synthesizer 100. The frequency synthesizer 100 includes a charge pump 102, a loop filter 104, a loop divider 106, an active and dual port VCO 110. An integrator 108 low pass filters a steering voltage to provide a low frequency path, in addition to the steering voltage, which provides a high frequency path. Both steering paths are connected to dual port VCO 110. The dual port VCO 110 is a single frequency generator which is controlled by two control signals. The dual port VCO 110, effectively provides the equivalent of a low frequency path 114 and a high frequency noise compensation path 112, both paths effectively merging 116 by superposition. The pseudo-third order dual steered frequency synthesizer includes an additional pole and zero (and thus is a fourth order synthesizer) which results from the availability of two steering voltage paths, a high frequency path and a low frequency path.

Abstract: A high gain wide-band width RF amplifier 120 with automatic bias supply regulation. The load supply is actively adjusted in response to the amplifier's output signal level. At small output signals effective load supply voltage is minimum and at larger output signals the effective load supply voltages is maximized. The amplifier 120 includes a differential pair of field effect transistors (FETs) 102, 104 connected at common source connection 106 and biased by current bias FET 108 which is connected between common source connection 106 and amplifier signal input RFIN. A bias voltage (VB1) is applied to the gate of bias device 108 and an automatic gain control voltage (VAGC) is applied to the gates of differential FET pair 102, 104. The automatic bias supply circuit 122 is an active load and includes resistors 124, 126, capacitor 128 and a differential amplifier 130. Capacitor 128 is connected between the negative input 132 and the output 134 of differential amplifier 130.

Abstract: A multiphase voltage controlled oscillator (e.g., a quadrature VCO) 100, which includes multiple voltage controllable transconductance phase drivers 102, 104, 106 and 108. The output of each voltage controllable transconductance phase driver 102, 104, 106, 108 supplies one of 4 oscillator phases and receives 2 of the 4 phases as inputs. Each of the voltage controllable transconductance phase drivers 102, 104, 106 and 108 corresponds to a pair of controllable transconductance inverting amplifiers 132, 134, 136, 138. The controllable transconductance inverting amplifiers may be a simple inverter 150 that includes N-type FET (NFET) 152 and P-type FET (PFET) 154. Transconductance is controlled in the simple inverter by raising or lowering supply voltage (Vdd) levels. A more complex controllable transconductance inverting amplifier may be used, replacing PFET 154 with series connected PFETs 164, 166. The gate of one PFET 166 is controlled by a bias control voltage VCON.

Abstract: A regulation circuit, incorporated in a single integrated circuit with a first circuit load, which as an input coupled to a power supply which produces a source voltage, and a first output coupled to the first circuit load. The regulation circuit comprises an input capacitor for reducing the magnitude of a voltage change at the first output, and at least a first voltage regulator for producing a predetermined voltage at the first load.

Abstract: A single ended input differential output amplifier (100) and integrated circuit including such an amplifier (100). A pair of load resistors (102, 104) are connected between a supply voltage (Vdd) and differential outputs OUTP and OUTM. An inductor (106) is connected between input RFIN and a source bias voltage VBs. A first field effect transistor (FET) (108) is connected, drain to source, between load resistor (102) at output OUTP and inductor (106) at RFIN. A second FET (110) is connected, drain to source, between the second load resistor (104) at output OUTM and the source bias voltage VBS. A gate bias voltage VBg is connected to the gate of FET (108) and through resistor (112) to the gate of FET (110). A coupling capacitor (114) is connected between the input RFIN and the gate of FET (110).

Abstract: A buck or boost (BOB) power converter circuit. A buck converter is cascaded with a boost converter to form a buck or boost circuit (20). The BOB converter is controlled by a controller (26) such that only the buck or boost converter is operating at any given time. A reference signal Vref can be applied to the controller (26) such that the output voltage from the converter closely tracks the reference signal. Positive and negative ramp signals are generated and an error feedback signal is compared with the ramp signals to control the output in accord with Vref. This is useful in application of the output voltage as the power supply to an RF Power Amplifier (16) so that the reference signal can represent the envelope of a signal to be transmitted and the RF PA (16) can operate at high efficiency.

Abstract: A method (200) and device (100) provide an efficient linear power amplifier that generates a variable-envelope radio frequency RF signal. The method includes the steps of: A) using an efficient envelope-following unit to output a supply voltage in accordance with a variable envelope of an input baseband signal, wherein using the efficient envelope-following unit includes: 1) using a bandwidth-limiting mapping unit to determine a reference signal based on the baseband signal; and 2) using an envelope-tracking power converter to output a supply voltage, responsive to the reference signal, to the linear RF power amplifier; B) providing an RF input signal with amplitude and phase information to a linear RF power amplifier; and C) using the linear RF power amplifier to output a power-efficient amplified variable-envelope RF signal with substantially a same amplitude and phase information as the RF input signal.

Abstract: A method (300, 400), device (100, 200), phone (200) and base station (200) provide an efficient tracking power converter for variable signals. The tracking power converter includes a feedforward feedback control unit that is coupled to receive a reference signal and to receive at least one feedback signal and is used for determining an optimal control signal in accordance with a predetermined scheme, a pulse width modulation unit that is coupled to the feedforward feedback control unit and is used for modifying a duty ratio to provide a switching signal, and a power converter that is coupled to the pulse width modulation unit and to a power source and is used for providing the dynamic variable output signal.

Abstract: A fast and efficient median search method and filter searches a dynamically changing time-ordered list of data samples for a data sample representing the arithmetic median of the list. Embodiments include a method to reduce the number of memory access operations to 2N and a method to reduce the number of memory access operations to N, where N is the number of data samples searched. The described approach includes providing a circular list of N data samples including an incoming data sample replacing an outgoing data sample, and a median data sample. Then, updating the median data sample dependent on magnitudes of the incoming data sample, the median data sample, and the outgoing data sample.

Abstract: A digital-to-analog converter with cascaded coarse and fine resistor divider strings. The fine resistor string contains 2.sup.N or more resistor segments controlled by N number of fine divider control bits. Resistors located at each end of the fine divider string are a fraction of the nominal value for the remaining fine divider resistor segments. The on-resistance of switches coupling the coarse and fine resistor divider strings is less than or equal to a predetermined fraction of the nominal value for the fine divider resistor segments to minimize contributions to linearity error. The DAC uses all CMOS devices including NMOS and PMOS switches which utilize approximately the full rail-to-rail voltage of the voltage source without the use of additional amplifiers. The DAC provides linearity of about one-fourth LSB.

Abstract: A temperature compensated crystal oscillator with an improved phase noise characteristic and a fast start up time includes a large time constant low-pass filter coupled to a temperature compensation circuit. At start up the low pass filter is effectively bypassed to enable the temperature compensation voltage and oscillator output frequency to settle quickly. A capacitance in the low-pass filter is precharged by a precharge circuit to match the temperature compensation voltage without disturbing the temperature compensation circuit and the concurrent settling of the oscillator. When the capacitance is fully charged, the low-pass filter is enabled without unsettling the oscillator output frequency.

Abstract: A circuit (34) for data recovery in a wireless powered communication device (10) obviates the need for the costly high power consumption filters of prior art devices by deriving a clock signal from the power coil (18), and then sampling the data coil (20) signal with the derived sampling clock. The step of deriving a clock signal from the power signal causes the component of the power signal present on the data signal to be aliased to DC which is then easily rejected with a low order high pass or bandpass filter (38). Furthermore, the data signal may be amplified to a desired level suitable for amplitude discrimination by a simple comparator circuit (40) with hysteresis. Demodulation of the data signal is easily accomplished in the digital domain using a digital demodulator (32).

Abstract: A communication device including a plurality of frequency synthesizers (24, 28, 30). At least one of the frequency synthesizers (24) is driven with a reference frequency from a crystal oscillator (58). The at least one frequency synthesizer (24) includes a phase locked loop with a fractional-N divider (48) which is programmed by a control circuit (64) to vary as a function of temperature compensation, frequency compensation, and a frequency multiplication factor. The output (46) of the at least one frequency synthesizer (24) is used to provide a compensated reference frequency input for the remaining frequency synthesizers (28, 30). The radio provides all the frequency synthesizers (24, 28, 30) with temperature and frequency compensation using a reference frequency from a crystal oscillator (58) and only one high resolution frequency compensating synthesizer (24).

Abstract: In a communication unit a receiver (104) receives a modulated signal (118), and produces a received signal (120) having a parameter. The receiver (104) has a discontinuous receive mode of operation, wherein the receiver (104) is permitted to be turned on and off. Receiver circuitry (105) receives the received signal (120), and produces an output signal (124) having a parameter. A controller (110) adjusts a value of the parameter of the output signal (124), responsive to a value of the parameter of the received signal (120), during the times when the receiver (140) is turned on; and holds the value of the parameter of the output signal (124), responsive to the value of the parameter of the received signal (120), at the time when the receiver (104) is turned off. The present invention advantageously minimizes the turn on time for the receiver (104) operating in a discontinuous receive mode to save current drain.