Abstract: A floating-point in-memory multiplication device achieving one-step floating-point multiplication operation is disclosed. The device performs multiplication on a multiplicand and a multiplier and generates a first product. Each of the multiplicand, the multiplier and the first product is a binary floating-point number in IEEE 754 format and contains a sign bit, a q-bit exponent and a (p?1)-bit significand. The device comprises a XOR gate device, a decoder circuit, an adder circuit, a binary in-memory multiplier circuit and an encoder circuit. The XOR gate device receives the sign bits of the multiplicand and the multiplier to generate a sign bit of the first product. The adder circuit adds up the q-bit exponents of the multiplicand and the multiplier to generate a (q+1)-bit temporary exponent. The binary in-memory multiplier circuit performs multiplication on a first and a second p-bit significands to generate a 2p-bit second product.

Abstract: An example of a biotin-streptavidin cleavage composition includes a formamide reagent and a salt buffer. The formamide reagent is present in the biotin-streptavidin cleavage composition in an amount ranging from about 10% to about 50%, based on a total volume of the biotin-streptavidin cleavage composition. The salt buffer makes up the balance of the biotin-streptavidin cleavage composition. In some examples, the biotin-streptavidin cleavage composition is used to cleave library fragments from a solid support. In other examples, other mechanisms are used to cleave library fragments from a solid support.

Abstract: The neuron Logic Gate Metal-Oxide-Semiconductor (?LGMOS) circuits to mimic neurons' “integrate-and-fire” behaviors in biological neural network system can be fabricated with industry Complementary Metal-Oxide Semiconductor (CMOS) logic process technology, with which digital computational circuits are fabricated. A processing system having analog ?LGMOS circuits, conversion circuitry and digital circuits optimized for power and cost for varieties of applications can be then fabricated with the same CMOS logic process technology for IC chips. Meanwhile analog ?LGMOS circuits inspired from biological neural network systems can be simulated, designed, and fabricated for IC chips for the applications of biomedical fields.

Abstract: An example of a biotin-streptavidin cleavage composition includes a formamide reagent and a salt buffer. The formamide reagent is present in the biotin-streptavidin cleavage composition in an amount ranging from about 10% to about 50%, based on a total volume of the biotin-streptavidin cleavage composition. The salt buffer makes up the balance of the biotin-streptavidin cleavage composition. In some examples, the biotin-streptavidin cleavage composition is used to cleave library fragments from a solid support. In other examples, other mechanisms are used to cleave library fragments from a solid support.

Abstract: A method for forming floating gates in a non-volatile memory array is disclosed, comprising: patterning and etching portions of a hard-mask dielectric layer, a conductive layer and a tunneling oxide layer to define stacked structures over a substrate; conformally depositing a spacer dielectric layer over the substrate; etching a portion of the spacer dielectric layer to form spacers along sidewalls of each stacked structure; etching a portion of the substrate to form trenches so that the trenches and the stacked structures are alternately arranged in each row; and, growing liners on silicon walls of the trenches. Here, the hard-mask dielectric layer and the spacer dielectric layer comprise an oxidation-blocking material. Accordingly, the poly-silicon floating-gates are encapsulated in the hard-mask dielectric layer and the spacers such that the shapes of floating-gates and the tunneling oxide thickness are well preserved.

Abstract: A method is provided for diagnosing a failure on an aircraft that includes aircraft systems and monitors configured to report effects of failure modes of the aircraft systems. The method includes receiving a fault report that indicates one or more of the monitors that reported the effects of a failure mode in an aircraft system of the aircraft systems, and accessing a fault pattern library that describes relationships between possible failure modes and patterns of those of the monitors configured to report the effects of the possible failure modes. The method also includes diagnosing the failure mode of the aircraft system from the one or more of the monitors that reported, and using the fault pattern library and a greedy selection algorithm, determining a maintenance action for the failure mode; and generating a maintenance message including at least the maintenance action.

Abstract: A memory device is disclosed, comprising a 4T-SRAM cell and a read circuit. The 4T-SRAM cell comprising two P-type MOSFET devices for a data bit storage and two N-type MOSFET for accessing switches has benefits of less numbers of MOSFET devices for smaller cell size and low leakage current than the conventional 6T-SRAM cell. The read circuit comprises a latch and a discharge device. The latch with two output nodes is coupled between a supply voltage rail and a ground voltage rail. The discharge device is coupled to the two output nodes, a bit line pair and the ground voltage rail. Since one of two storage nodes for the 4T-SRAM cell is floating, the stored data in the 4T-SRAM cell is vulnerable for conventional read operations. The read circuit of the invention resolves the vulnerability issue of the 4T-SRAM cell.

Abstract: A Super Short Channel NOR-type (SSC NOR) flash array is disclosed. Upon the new Channel Induced Ternary Electron programming scheme for resolving the punch-through issue caused by the gate short channel of NVM cell devices, the gate length of NVM cell devices can be further shrunk below 100 nm for NOR flash array. The cell device of SSC NOR flash can be then scaled down to achieve the minimum cell sizes between 4F2 to 5F2, where F is the minimum feature size of a process technology node below 100 nm. In comparison with conventional NOR flash, the SSC NOR flash improves memory density resulting in cost reduction per bit storage. While on the benefit of increasing memory density and storage cost reduction, the invention preserves the typical NOR-type flash advantages over NAND flash on fast nanosecond-range access time, low operating voltages, and high reliability.

Abstract: Nucleic acid amplification techniques are disclosed. Embodiments include generating concatenated nucleic acids using rolling circle amplification of templates, e.g., starting from a cDNA of a full-length mRNA or from synthetic templates, and sequencing and/or detecting the concatenated nucleic acids. In some embodiments, the technology disclosed includes amplification reactions that include CRISPR-Cas interactions that generate primers as a result of the CRISPR-Cas interactions, whereby primers are in turn used as part of detectable amplification reactions. The disclosed amplification techniques may use synthetic oligonucleotides or primers.

Abstract: Inspired by the processing methods of biologic brains, we construct a network of multiple configurable non-volatile memory arrays connected with bus-lines as a neuromorphic code processor for code processing. In contrast to the Von-Neumann computing architectures applying the multiple computations for code vector manipulations, the neuromorphic code processor of the invention processes codes according to their configured codes stored in the non-volatile memory arrays. Similar to the brain processor, the neuromorphic code processor applies the one-step feed-forward processing in parallel resulting in a dramatic power reduction compared with the computational methods in the conventional computer processors.

Abstract: A Super Short Channel NOR-type (SSC NOR) flash array is disclosed. Upon the new Channel Induced Ternary Electron programming scheme for resolving the punch-through issue caused by the gate short channel of NVM cell devices, the gate length of NVM cell devices can be further shrunk below 100 nm for NOR flash array. The cell device of SSC NOR flash can be then scaled down to achieve the minimum cell sizes between 4F2 to 5F2, where F is the minimum feature size of a process technology node below 100 nm. In comparison with conventional NOR flash, the SSC NOR flash improves memory density resulting in cost reduction per bit storage. While on the benefit of increasing memory density and storage cost reduction, the invention preserves the typical NOR-type flash advantages over NAND flash on fast nanosecond-range access time, low operating voltages, and high reliability.

Abstract: Some embodiments of the methods and compositions provided herein relate to the selective cleavage of a target nucleic acid. Some such embodiments include the selective cleavage of a target nucleic acid that is associated with a DNA-binding protein or comprises a methylated CpG island, with a recombinant nuclease. In some embodiments, the DNA-binding protein comprises a chromatin protein. Some embodiments also include the enrichment of non-target nucleic acids in a sample by selective cleavage of target nucleic acids in the sample, and removal of the cleaved target nucleic acids from the sample.

Abstract: For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.

Abstract: Some embodiments of the methods and compositions provided herein relate to the selective cleavage of a target nucleic acid. Some such embodiments include the selective cleavage of a target nucleic acid that is associated with a DNA-binding protein or comprises a methylated CpG island, with a recombinant nuclease. In some embodiments, the DNA-binding protein comprises a chromatin protein. Some embodiments also include the enrichment of non-target nucleic acids in a sample by selective cleavage of target nucleic acids in the sample, and removal of the cleaved target nucleic acids from the sample.

Abstract: Embodiments of the methods and compositions provided herein relate to the selective cleavage of target nucleic acids. Some embodiments include recombinase-mediated selective cleavage of target nucleic acids with single-stranded nucleic acid probes and a recombinase. Some embodiments also include the enrichment of non-target nucleic acids in a sample by selective cleavage of target nucleic acids in the sample, and removal of the cleaved target nucleic acids from the sample.

Abstract: In-memory arithmetic processors for the “n-bit” by “n-bit” multiplication, the “n-bit” by “n-bit” addition, and the “n-bit” by “n-bit” subtraction operations are disclosed. The in-memory arithmetic processors of the invention can obtain the operational resultant integer in the binary format for two inputted integers represented by two “n-bit” binary codes in one-step processing with no sequential multiple-step operations as for the conventional arithmetic binary processors. The in-memory arithmetic processors are implemented by a 2-dimensional memory array with X and Y decoding for the two inputted operational integers in the arithmetic binary operations.

Abstract: Embodiments of the methods and compositions provided herein relate to the selective cleavage of target nucleic acids. Some embodiments include recombinase-mediated selective cleavage of target nucleic acids with single-stranded nucleic acid probes and a recombinase. Some embodiments also include the enrichment of non-target nucleic acids in a sample by selective cleavage of target nucleic acids in the sample, and removal of the cleaved target nucleic acids from the sample.

Abstract: An in-memory digital processor, Perpetual Digital Perceptron (PDP), is disclosed. The digital in-memory processor of the invention processes the input digital information according to a database of the digital content data stored/hardwired in the Content Read Only Memory (CROM) array and outputs the correspondent digital response data stored/hardwired in the Response Read Only Memory (RROM) array. The PDP is the hardwired digital in-memory processor without re-configuration capability and similar to the instinct functions of biological hardwired brains without re-shaping their neuromorphic structures from training and learning.

Abstract: A method is provided for diagnosing a failure on an aircraft that includes aircraft systems and monitors configured to report effects of failure modes of the aircraft systems. The method includes receiving a fault report that indicates one or more of the monitors that reported the effects of a failure mode in an aircraft system of the aircraft systems, and accessing a fault pattern library that describes relationships between possible failure modes and patterns of those of the monitors configured to report the effects of the possible failure modes. The method also includes diagnosing the failure mode of the aircraft system from the one or more of the monitors that reported, and using the fault pattern library and a greedy selection algorithm, determining a maintenance action for the failure mode; and generating a maintenance message including at least the maintenance action.

Abstract: The multi-digit binary in-memory multiplication devices are disclosed. The multi-digit binary in-memory multiplication devices of the invention can dramatically reduce the operational steps in comparison with the conventional binary multiplier device. In one embodiment with the expense of more hardware, the in-memory multiplication device can achieve one single step operation. Consequently, the multi-digit binary in-memory multiplication device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU), registers, and memory units.