Abstract: An antenna structure includes a substrate, a plurality of reflective plates, a grounding plate, a radiating member, a signal feeding via and a plurality of conductive vias. The substrate has opposite first and second surfaces and comprises liquid crystal polymer. The reflective plates are arrayed on the first surface of the substrate. The grounding plate is disposed on the second surface of the substrate and overlapped with the reflective plates in a normal direction of the substrate. The grounding plate further includes an opening. The radiating member is disposed on the first surface of the substrate and physically separated from the reflective plates. The signal feeding via is coupled with the radiating member and penetrates through the substrate to be exposed in the opening of the grounding plate. The conductive vias penetrate through the substrate and respectively connect the reflective plates and the grounding plate.

Abstract: Systems and methods are described for merging customer profiles, such as may be implemented by a computer-implemented contact center service. In some aspects, a subset of profiles may be determined that satisfy merging criteria, where individual profiles include a plurality of data fields. At least one value in a first data field that conflicts between at least two profiles may be identified. Next a merged value may be selected for the first data field based on data deduplication criteria, where the data deduplication criteria includes at least one indicator of accuracy of values of the plurality of data fields. As a result of a determination that at least the subset of profiles of the group of profiles meet the merging criteria, at least the subset of profiles may be combined into a combined profile using the merged value.

Abstract: Techniques and apparatuses directed to component shielding are described in this document. A first aspect relates to a system including a printed circuit board (PCB) oriented along a first plane, a device on the PCB, and a component shield having a wall structure oriented perpendicular to the first plane and a cover structure connected to the wall structure. The system includes a housing structure oriented along a second plane that is substantially parallel to the first plane. The first and second planes define a shielded space within which the component shield and the device reside. The system further includes a shielding layer residing at least partially between the cover and housing structures. The shielding layer has an irregular cross-section along a fourth plane perpendicular to at least one of the first or second planes and a third plane. The irregular cross-section includes a protrusion that extends from the third plane.

Abstract: An antenna system includes: a patch antenna element disposed at a first level of the antenna system; an energy coupler configured and coupled to the patch antenna element to transfer energy between the patch antenna element and a front-end circuit; a ground conductor disposed at a second level of the antenna system, the patch antenna element and the ground conductor being disposed a separation distance away from each other and bounding respective sides of a volume defined by a projection, normal to a surface of the patch antenna element, of the patch antenna element to the ground conductor; and a floating conductor that is displaced from the ground conductor and the patch antenna element, the floating conductor comprising a body extending over a portion of the separation distance outside of, and in close proximity to, the volume.

Abstract: Electronic devices, displays, and methods are provided for operating an electronic display in coexistence with sensors that could be adversely impacted by the operation of the electronic display. An electronic device may include an electronic display and a sensor. The electronic display may display image content by light emission during an emission period and periodically enter a quiet period in which the light emission of the electronic display is turned off. The sensor may perform sensing operations during the quiet period without interference from the operation of the electronic display.

Abstract: A multi-band filter includes a circuit board, a first resonator, a second resonator, and a coupling element configured to couple the first resonator with the second resonator. The coupling element includes a first coupling capacitor, a second coupling capacitor, a first short-circuited stub and a second short-circuited stub. The first coupling capacitor has two terminals electrically connected to the first portion of the first resonator and the first portion of the second resonator respectively. The second coupling capacitor has two terminals electrically connected to the second portion of the first resonator and the second portion of the second resonator respectively. The first short-circuited stub is electrically connected to the first coupling capacitor and a ground plane. The second short-circuited stub is electrically connected to the second coupling capacitor and a ground plane.

Abstract: A side step assembly can be installed on a side-by-side all-terrain vehicle. The side step kit can include a vehicle step stay and a side step cover. The vehicle step stay can include a first stay member and a second stay member. The first stay member can be configured to be attached onto a frame assembly of the vehicle. The second stay member can be configured to be attached to the first stay member and onto the frame assembly. The side step cover can be supported by the vehicle step stay when the vehicle step stay is connected to the frame assembly and the side step cover is mounted on the vehicle step stay. The side step cover can include a tread surface extending above and along the first stay member when the side step cover is mounted on the vehicle step stay.

Abstract: A dialysis machine includes a user interface for providing visual information and/or spoken information to a user. For example, in some implementations, the user interface may be configured to provide visual information related to an action, such as showing the action being partially or fully completed, and a speaker can provide spoken instructions to assist the user in machine set-up, calibration and/or operation. Such instructions can be particularly useful in a home dialysis setting. In some implementations, the speaker can provide spoken alarms that are related to alarm conditions. The spoken alarms may include patient and/or dialysis machine identifying information. The verbosity of the spoken instructions and/or the spoken alarms may be adjustable, and both may be accompanied by visual information displayed by the dialysis machine (e.g. visual alarms, images and/or video).

Abstract: Some embodiments of the methods and compositions provided herein relate to the selective cleavage of a target nucleic acid. Some such embodiments include the selective cleavage of a target nucleic acid that is associated with a DNA-binding protein or comprises a methylated CpG island, with a recombinant nuclease. In some embodiments, the DNA-binding protein comprises a chromatin protein. Some embodiments also include the enrichment of non-target nucleic acids in a sample by selective cleavage of target nucleic acids in the sample, and removal of the cleaved target nucleic acids from the sample.

Abstract: Provided is a marker composition for predicting the prognosis of cancer and a method for predicting the prognosis of cancer using same and, more particularly, to a marker composition for predicting the prognosis of cancer comprising an agent for measuring an expression level of mRNA or protein thereof of at least one gene selected from the group consisting of ESR1, BEST1, ACTA2, HIPK2, IGSF9, ASCC2, JUN, PPP2R5A, SMAD3, CREBBP, EP300, and DDX5, to a method for predicting the prognosis of cancer using same, and to a method for providing information for determining a strategy for treating cancer.

Abstract: For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.

Abstract: Some embodiments of the methods and compositions provided herein relate to the selective cleavage of a target nucleic acid. Some such embodiments include the selective cleavage of a target nucleic acid that is associated with a DNA-binding protein or comprises a methylated CpG island, with a recombinant nuclease. In some embodiments, the DNA-binding protein comprises a chromatin protein. Some embodiments also include the enrichment of non-target nucleic acids in a sample by selective cleavage of target nucleic acids in the sample, and removal of the cleaved target nucleic acids from the sample.

Abstract: Embodiments of the methods and compositions provided herein relate to the selective cleavage of target nucleic acids. Some embodiments include recombinase-mediated selective cleavage of target nucleic acids with single-stranded nucleic acid probes and a recombinase. Some embodiments also include the enrichment of non-target nucleic acids in a sample by selective cleavage of target nucleic acids in the sample, and removal of the cleaved target nucleic acids from the sample.

Abstract: In-memory arithmetic processors for the “n-bit” by “n-bit” multiplication, the “n-bit” by “n-bit” addition, and the “n-bit” by “n-bit” subtraction operations are disclosed. The in-memory arithmetic processors of the invention can obtain the operational resultant integer in the binary format for two inputted integers represented by two “n-bit” binary codes in one-step processing with no sequential multiple-step operations as for the conventional arithmetic binary processors. The in-memory arithmetic processors are implemented by a 2-dimensional memory array with X and Y decoding for the two inputted operational integers in the arithmetic binary operations.

Abstract: Embodiments of the methods and compositions provided herein relate to the selective cleavage of target nucleic acids. Some embodiments include recombinase-mediated selective cleavage of target nucleic acids with single-stranded nucleic acid probes and a recombinase. Some embodiments also include the enrichment of non-target nucleic acids in a sample by selective cleavage of target nucleic acids in the sample, and removal of the cleaved target nucleic acids from the sample.

Abstract: An in-memory digital processor, Perpetual Digital Perceptron (PDP), is disclosed. The digital in-memory processor of the invention processes the input digital information according to a database of the digital content data stored/hardwired in the Content Read Only Memory (CROM) array and outputs the correspondent digital response data stored/hardwired in the Response Read Only Memory (RROM) array. The PDP is the hardwired digital in-memory processor without re-configuration capability and similar to the instinct functions of biological hardwired brains without re-shaping their neuromorphic structures from training and learning.

Abstract: A method is provided for diagnosing a failure on an aircraft that includes aircraft systems and monitors configured to report effects of failure modes of the aircraft systems. The method includes receiving a fault report that indicates one or more of the monitors that reported the effects of a failure mode in an aircraft system of the aircraft systems, and accessing a fault pattern library that describes relationships between possible failure modes and patterns of those of the monitors configured to report the effects of the possible failure modes. The method also includes diagnosing the failure mode of the aircraft system from the one or more of the monitors that reported, and using the fault pattern library and a greedy selection algorithm, determining a maintenance action for the failure mode; and generating a maintenance message including at least the maintenance action.

Abstract: The multi-digit binary in-memory multiplication devices are disclosed. The multi-digit binary in-memory multiplication devices of the invention can dramatically reduce the operational steps in comparison with the conventional binary multiplier device. In one embodiment with the expense of more hardware, the in-memory multiplication device can achieve one single step operation. Consequently, the multi-digit binary in-memory multiplication device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU), registers, and memory units.

Abstract: In an example, a target material is immobilized on two opposed sequencing surfaces of a flow cell using first and second fluids. The first fluid has a density less than a target material density and the second fluid has a density greater than the target material density; or the second fluid has a density less than the target material density and the first fluid has a density greater than the target material density. The first fluid (including the target material) is introduced into the flow cell, whereby at least some of the target material becomes immobilized by capture sites on one of the sequencing surfaces. The first fluid and non-immobilized target material are removed. The second fluid (including target material) is introduced into the flow cell, whereby at least some of the target material becomes immobilized by capture sites on another of the sequencing surfaces.

Abstract: The Non-Volatile Arithmetic Memory Operator (NV-AMO) including a non-volatile memory cell for storing non-volatile data and a first input terminal for receiving volatile variable data is applied to perform the arithmetic operations over the volatile variable data and the non-volatile data. The NV-AMO can also be configured multiple-times for new computations. The constructions of NV-AMO in Arithmetic Logic Units (ALU) can be applied in DSP (Digital Signal Processor) computations and DNN (Deep Neural Network) computations.