Patents by Inventor Lee Wang

Lee Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240082466
    Abstract: A dialysis machine includes a user interface for providing visual information and/or spoken information to a user. For example, in some implementations, the user interface may be configured to provide visual information related to an action, such as showing the action being partially or fully completed, and a speaker can provide spoken instructions to assist the user in machine set-up, calibration and/or operation. Such instructions can be particularly useful in a home dialysis setting. In some implementations, the speaker can provide spoken alarms that are related to alarm conditions. The spoken alarms may include patient and/or dialysis machine identifying information. The verbosity of the spoken instructions and/or the spoken alarms may be adjustable, and both may be accompanied by visual information displayed by the dialysis machine (e.g. visual alarms, images and/or video).
    Type: Application
    Filed: September 1, 2023
    Publication date: March 14, 2024
    Inventors: Lee Daniel Tanenbaum, Fei Wang, Mario Gumina, Thomas Merics, Eric Hoffstetter, Matthew J. Doyle, Aleo Nobel Mok, Wayne Raiford
  • Publication number: 20240076717
    Abstract: Some embodiments of the methods and compositions provided herein relate to the selective cleavage of a target nucleic acid. Some such embodiments include the selective cleavage of a target nucleic acid that is associated with a DNA-binding protein or comprises a methylated CpG island, with a recombinant nuclease. In some embodiments, the DNA-binding protein comprises a chromatin protein. Some embodiments also include the enrichment of non-target nucleic acids in a sample by selective cleavage of target nucleic acids in the sample, and removal of the cleaved target nucleic acids from the sample.
    Type: Application
    Filed: August 15, 2023
    Publication date: March 7, 2024
    Inventor: Clifford Lee Wang
  • Publication number: 20240068044
    Abstract: Provided is a marker composition for predicting the prognosis of cancer and a method for predicting the prognosis of cancer using same and, more particularly, to a marker composition for predicting the prognosis of cancer comprising an agent for measuring an expression level of mRNA or protein thereof of at least one gene selected from the group consisting of ESR1, BEST1, ACTA2, HIPK2, IGSF9, ASCC2, JUN, PPP2R5A, SMAD3, CREBBP, EP300, and DDX5, to a method for predicting the prognosis of cancer using same, and to a method for providing information for determining a strategy for treating cancer.
    Type: Application
    Filed: December 14, 2021
    Publication date: February 29, 2024
    Inventors: Tae Hyun HWANG, Sunho PARK, Jae Ho CHEONG, Sung Hak LEE, Chung-Kang Sam WANG, Ryan Matthew POREMBKA
  • Patent number: 11825652
    Abstract: For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: November 21, 2023
    Assignee: FLASHSILICON INCORPORATION
    Inventor: Lee Wang
  • Patent number: 11773427
    Abstract: Some embodiments of the methods and compositions provided herein relate to the selective cleavage of a target nucleic acid. Some such embodiments include the selective cleavage of a target nucleic acid that is associated with a DNA-binding protein or comprises a methylated CpG island, with a recombinant nuclease. In some embodiments, the DNA-binding protein comprises a chromatin protein. Some embodiments also include the enrichment of non-target nucleic acids in a sample by selective cleavage of target nucleic acids in the sample, and removal of the cleaved target nucleic acids from the sample.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: October 3, 2023
    Assignee: Illumina, Inc.
    Inventor: Clifford Lee Wang
  • Publication number: 20230287477
    Abstract: Embodiments of the methods and compositions provided herein relate to the selective cleavage of target nucleic acids. Some embodiments include recombinase-mediated selective cleavage of target nucleic acids with single-stranded nucleic acid probes and a recombinase. Some embodiments also include the enrichment of non-target nucleic acids in a sample by selective cleavage of target nucleic acids in the sample, and removal of the cleaved target nucleic acids from the sample.
    Type: Application
    Filed: April 11, 2023
    Publication date: September 14, 2023
    Inventor: Clifford Lee Wang
  • Patent number: 11662980
    Abstract: In-memory arithmetic processors for the “n-bit” by “n-bit” multiplication, the “n-bit” by “n-bit” addition, and the “n-bit” by “n-bit” subtraction operations are disclosed. The in-memory arithmetic processors of the invention can obtain the operational resultant integer in the binary format for two inputted integers represented by two “n-bit” binary codes in one-step processing with no sequential multiple-step operations as for the conventional arithmetic binary processors. The in-memory arithmetic processors are implemented by a 2-dimensional memory array with X and Y decoding for the two inputted operational integers in the arithmetic binary operations.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: May 30, 2023
    Assignee: FLASHSILICON INCORPORATION
    Inventor: Lee Wang
  • Patent number: 11649481
    Abstract: Embodiments of the methods and compositions provided herein relate to the selective cleavage of target nucleic acids. Some embodiments include recombinase-mediated selective cleavage of target nucleic acids with single-stranded nucleic acid probes and a recombinase. Some embodiments also include the enrichment of non-target nucleic acids in a sample by selective cleavage of target nucleic acids in the sample, and removal of the cleaved target nucleic acids from the sample.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: May 16, 2023
    Assignee: Illumina, Inc.
    Inventor: Clifford Lee Wang
  • Patent number: 11600320
    Abstract: An in-memory digital processor, Perpetual Digital Perceptron (PDP), is disclosed. The digital in-memory processor of the invention processes the input digital information according to a database of the digital content data stored/hardwired in the Content Read Only Memory (CROM) array and outputs the correspondent digital response data stored/hardwired in the Response Read Only Memory (RROM) array. The PDP is the hardwired digital in-memory processor without re-configuration capability and similar to the instinct functions of biological hardwired brains without re-shaping their neuromorphic structures from training and learning.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: March 7, 2023
    Assignee: FLASHSILICON INCORPORATION
    Inventor: Lee Wang
  • Publication number: 20220388689
    Abstract: A method is provided for diagnosing a failure on an aircraft that includes aircraft systems and monitors configured to report effects of failure modes of the aircraft systems. The method includes receiving a fault report that indicates one or more of the monitors that reported the effects of a failure mode in an aircraft system of the aircraft systems, and accessing a fault pattern library that describes relationships between possible failure modes and patterns of those of the monitors configured to report the effects of the possible failure modes. The method also includes diagnosing the failure mode of the aircraft system from the one or more of the monitors that reported, and using the fault pattern library and a greedy selection algorithm, determining a maintenance action for the failure mode; and generating a maintenance message including at least the maintenance action.
    Type: Application
    Filed: March 31, 2022
    Publication date: December 8, 2022
    Inventors: Jason M. Keller, Lee Wang, James M. Ethington
  • Patent number: 11461074
    Abstract: The multi-digit binary in-memory multiplication devices are disclosed. The multi-digit binary in-memory multiplication devices of the invention can dramatically reduce the operational steps in comparison with the conventional binary multiplier device. In one embodiment with the expense of more hardware, the in-memory multiplication device can achieve one single step operation. Consequently, the multi-digit binary in-memory multiplication device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU), registers, and memory units.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: October 4, 2022
    Assignee: FLASHSILICON INCORPORATION
    Inventor: Lee Wang
  • Publication number: 20220195519
    Abstract: In an example, a target material is immobilized on two opposed sequencing surfaces of a flow cell using first and second fluids. The first fluid has a density less than a target material density and the second fluid has a density greater than the target material density; or the second fluid has a density less than the target material density and the first fluid has a density greater than the target material density. The first fluid (including the target material) is introduced into the flow cell, whereby at least some of the target material becomes immobilized by capture sites on one of the sequencing surfaces. The first fluid and non-immobilized target material are removed. The second fluid (including target material) is introduced into the flow cell, whereby at least some of the target material becomes immobilized by capture sites on another of the sequencing surfaces.
    Type: Application
    Filed: December 11, 2020
    Publication date: June 23, 2022
    Inventors: Jeffrey S. Fisher, Tarun Kumar Khurana, Mathieu Lessard-Viger, Clifford Lee Wang, Yir-Shyuan Wu
  • Patent number: 11354098
    Abstract: The Non-Volatile Arithmetic Memory Operator (NV-AMO) including a non-volatile memory cell for storing non-volatile data and a first input terminal for receiving volatile variable data is applied to perform the arithmetic operations over the volatile variable data and the non-volatile data. The NV-AMO can also be configured multiple-times for new computations. The constructions of NV-AMO in Arithmetic Logic Units (ALU) can be applied in DSP (Digital Signal Processor) computations and DNN (Deep Neural Network) computations.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: June 7, 2022
    Assignee: SYNERGER INC.
    Inventor: Lee Wang
  • Publication number: 20220052065
    Abstract: For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.
    Type: Application
    Filed: October 29, 2021
    Publication date: February 17, 2022
    Inventor: Lee WANG
  • Publication number: 20220042078
    Abstract: The disclosure relates to methods, compositions, and kits for the identification and analysis of microorganisms in a sample using nucleoside or nucleotide analogs.
    Type: Application
    Filed: April 28, 2020
    Publication date: February 10, 2022
    Inventor: Clifford Lee Wang
  • Publication number: 20220012011
    Abstract: The multi-digit binary in-memory multiplication devices are disclosed. The multi-digit binary in-memory multiplication devices of the invention can dramatically reduce the operational steps in comparison with the conventional binary multiplier device. In one embodiment with the expense of more hardware, the in-memory multiplication device can achieve one single step operation. Consequently, the multi-digit binary in-memory multiplication device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU), registers, and memory units.
    Type: Application
    Filed: July 10, 2020
    Publication date: January 13, 2022
    Inventor: LEE WANG
  • Patent number: 11201162
    Abstract: For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 14, 2021
    Assignee: FLASHSILICON INCORPORATION
    Inventor: Lee Wang
  • Patent number: 11200029
    Abstract: The base-2n in-memory adder device mainly comprises Perpetual Digital Perceptron (PDP) in-memory adder with Read Only Memory (ROM) arrays for storing the binary sum codes of the addition table for processing the addition operations of two n-bit binary integer operands. Since the integer numbers can be represented by the binary codes of multiple digits of base-2n integer numbers, the base-2n in-memory adder device can iterate multiple times of the digit-additions to complete the binary code addition for two m-digit base-2n integer operands. Consequently, the base-2n in-memory adder device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU), registers, and memory units.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: December 14, 2021
    Assignee: FLASHSILICON INCORPORATION
    Inventor: Lee Wang
  • Publication number: 20210326109
    Abstract: The base-2n in-memory adder device mainly comprises Perpetual Digital Perceptron (PDP) in-memory adder with Read Only Memory (ROM) arrays for storing the binary sum codes of the addition table for processing the addition operations of two n-bit binary integer operands. Since the integer numbers can be represented by the binary codes of multiple digits of base-2n integer numbers, the base-2n in-memory adder device can iterate multiple times of the digit-additions to complete the binary code addition for two m-digit base-2n integer operands. Consequently, the base-2n in-memory adder device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU), registers, and memory units.
    Type: Application
    Filed: April 16, 2020
    Publication date: October 21, 2021
    Inventor: Lee WANG
  • Publication number: 20210324444
    Abstract: Some embodiments of the methods and compositions provided herein relate to the selective cleavage of a target nucleic acid. Some such embodiments include the selective cleavage of a target nucleic acid that is associated with a DNA-binding protein or comprises a methylated CpG island, with a recombinant nuclease. In some embodiments, the DNA-binding protein comprises a chromatin protein. Some embodiments also include the enrichment of non-target nucleic acids in a sample by selective cleavage of target nucleic acids in the sample, and removal of the cleaved target nucleic acids from the sample.
    Type: Application
    Filed: March 15, 2019
    Publication date: October 21, 2021
    Inventor: Clifford Lee Wang