Abstract: A 3-D Single Floating Gate Non-Volatile Memory (SFGNVM) device based on the 3-D fin Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is disclosed. The disclosed Non-Volatile Memory (NVM) device consists of a pair of semiconductor fins and one floating metal gate. The floating metal gate for storing electrical charges to alter the threshold voltage of the fin MOSFET crosses over the pair of semiconductor fins on top of coupling and tunneling dielectrics above the surfaces of the two semiconductor fins. One semiconductor fin with the same type impurity forms the control gate of the non-volatile memory device. The other semiconductor fin is doped with opposite type of impurity in the channel regions under the metal floating gate and with the same type of impurity in the source and drain regions on the sides of the crossed metal floating gate.

Abstract: Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.

Abstract: A 3-D Single Floating Gate Non-Volatile Memory (SFGNVM) device based on the 3-D fin Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is disclosed. The disclosed Non-Volatile Memory (NVM) device consists of a pair of semiconductor fins and one floating metal gate. The floating metal gate for storing electrical charges to alter the threshold voltage of the fin MOSFET crosses over the pair of semiconductor fins on top of coupling and tunneling dielectrics above the surfaces of the two semiconductor fins. One semiconductor fin with the same type impurity forms the control gate of the non-volatile memory device. The other semiconductor fin is doped with opposite type of impurity in the channel regions under the metal floating gate and with the same type of impurity in the source and drain regions on the sides of the crossed metal floating gate.

Abstract: Methods and systems for selecting advertisements to present to a user of a computing device are provided. An advertisement system selects advertisements to display to a user based on the serving area of candidate advertisements. The advertisement system selects those candidate advertisements whose serving area encompasses the user's current location. The advertisement system may also select candidate advertisements to present to a user based on a map area currently being displayed to the user. The advertisement system may filter the candidate advertisements based on the provider location being within the map area that is currently being displayed to the user.

Abstract: A switch linkage mechanism includes a self-holding solenoid, at least a linkage shaft, at least a twist bar and at least a copper strip set. When the twist bar is at a circuit-closed position, the copper strip set is electrically connected to the high-current circuit breaker. When a self-holding solenoid is activated to pull up a central axle of the self-holding solenoid, the central axle pulls a joint of the linkage shaft and the central axle, and then it pushes the twist bar to be rotated to an circuit-opened position, so that the twist bar stretches out the copper strip set to cause the switch linkage mechanism to be electrically disconnected from the large-current circuit breaker.

Abstract: A Dynamic Random Access Memory (DRAM) cell and a semiconductor Non-Volatile Memory (NVM) cell are incorporated into a single Non-Volatile Dynamic Random Access Memory (NVDRAM) cell. The NVDRAM cell is operated as the conventional DRAM cell for read, write, and refreshment on dynamic memory applications. Meanwhile the datum in the NVM cells can be directly loaded into the correspondent DRAM cells in the NVDRAM cell array without applying intermediate data amplification and buffering leading to high speed non-volatile data access. The datum in DRAM cells can be also stored back to the correspondent semiconductor NVM cells in the NVDRAM cells for the datum required for non-volatile data storage. The NVDRAM of the invention can provide both fast read/write function for dynamic memory and non-volatile memory storage in one unit memory cell.

Abstract: Systems and methods providing a list having one or more wedding services vendors. The systems and method determine a valid set of vendors based on one or more received input data. A score for each respective vendor of the valid set of vendors is determined using the received input data and input data weighting rules. One or more recommended vendors are provided based on the determined valid set of vendors and the respective score for each respective vendor of the valid set of vendors. The one or more recommended vendors may be from the same category or from different categories of vendors. Systems and methods are also presented for managing electronic communications for wedding services by providing interfaces for enabling a vendor to present an electronic storefront related to wedding services and for a vendor to manage client leads received by the electronic storefront.

Abstract: Complementary Electrical Erasable Programmable Read Only Memory (CEEPROM) is disclosed. CEEPROM cell comprises a pair of non-volatile memory elements and one access transistor. The two elements of the non-volatile memory pair are configured to be one with high electrical conductance and the other with low electrical conductance. The positive voltage VDD for digital value “1” and ground voltage VSS for digital value “0” are connected to the two input nodes of the two non-volatile elements respectively after configuration. The digital signal either VDD or VSS passed through the high conductance non-volatile memory element in the pair is directly accessed by the access transistor without applying a sense amplifier as the conventional EEPROM would require. Without sense amplifiers, the digital data in CEEPROM can be fast accessed. The power consumption and the silicon areas required for sense amplifiers can be saved as well.

Abstract: Structures and methods of converting Multi-Level Cell (MLC) Non-Volatile Memory (NVM) into multi-bit information are disclosed. In MLC NVM system, multi-bit information stored in NVM cell is represented by the states of NVM cell threshold voltage levels. In this disclosure, “P” states of NVM cell threshold voltage levels are divided into “N” groups of threshold voltage levels. Each group contains “M” states of multiple threshold voltage levels of NVM cells, where P=N×M. The “M” states of NVM cell threshold voltage levels in each group are sensed and resolved by applying one correspondent gate voltage to the group. By applying “N” multiple gate voltages, the whole “P” states of NVM cell threshold voltage levels can be sensed and efficiently converted into storing bits in the MLC NVM cells.

Abstract: Scalable Gate Logic Non-Volatile Memory (SGLNVM) devices fabricated with the conventional CMOS process is disclosed. Floating gates of SGLNVM with the minimal length and width of the logic gate devices form floating gate Metal-Oxide-Semiconductor Field Effect Transistor. The floating gates with the minimal gate length extend over silicon active areas to capacitively couple control gates embedded in silicon substrate (well) through an insulation dielectric. The embedded control gate is formed by a shallow semiconductor type opposite to the type of the silicon substrate or well. Plurality of SGLNVM devices are configured into a NOR-type flash array where a pair of SGLNVM devices share a common source electrode connected to a common ground line with two drain electrodes connected to two separate bitlines. The pairs of the NOR-type SGLNVM cells are physically separated and electrically isolated by dummy floating gates to minimize cell sizes.

Abstract: Various methods and systems are provided to facilitate the centralized storage and access of online incentives such as coupons redeemable at associated online marketplaces. In one example, merchants may provide incentive information to payment service providers that in turn may associate such information with user accounts maintained by the payment service providers. Payment service providers may permit users to view incentives associated with their user accounts, thereby providing users with a comprehensive way to manage incentives from a plurality of online merchants. In another example, merchants may advise users of previously registered incentives in response to user activities in relation to online marketplaces.

Abstract: Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.

Abstract: Dual Conducting Floating Spacer Metal Oxide Semiconductor Field Effect Transistors (DCFS MOSFETs) and methods for fabricate them using a process that is compatible with forming conventional MOSFETs are disclosed. A DCFS MOSFET can provide multi-bit storage in a single Non-Volatile Memory (NVM) memory cell. Like a typical MOSFET, a DCFS MOSFET includes a control gate electrode on top of a gate dielectric-silicon substrate, thereby forming a main channel of the device. Two electrically isolated conductor spacers are provided on both sides of the control gate and partially overlap two source/drain diffusion areas, which are doped to an opposite type to the conductivity type of the substrate semiconductor. The DCFS MOSFET becomes conducting when a voltage that exceeds a threshold is applied at the control gate and is coupled through the corresponding conducting floating spacer to generate an electrical field strong enough to invert the carriers near the source junction.

Abstract: A membrane filtration apparatus includes a frame, in which a plurality of membrane members, an aeration device, a cleaning device, and a jet device are provided. The cleaning device includes a rail mounted on the frame; an up frame engaging the rail to be moved in the rail, a plurality of cleaning wires respectively having an end connected to the up frame and respectively passing through a space between each two of the neighboring membrane members; and a low frame connected to opposite ends of the cleaning wires. A motor is provided to move the up frame so that the cleaning wires are reciprocating in the space to scratch the sludge off the membrane members.

Abstract: Various methods and systems are provided to facilitate the centralized storage and access of online incentives such as coupons redeemable at associated online marketplaces. In one example, merchants may provide incentive information to payment service providers that in turn may associate such information with user accounts maintained by the payment service providers. Payment service providers may permit users to view incentives associated with their user accounts, thereby providing users with a comprehensive way to manage incentives from a plurality of online merchants. In another example, merchants may advise users of previously registered incentives in response to user activities in relation to online marketplaces.

Abstract: Non-Volatile Static Random Access Memory (NVSRAM) cell devices applying only one single non-volatile element embedded in a conventional Static Random Access Memory (SRAM) cell are disclosed. The NVSRAM cell devices can be integrated into a compact cell array. The NVSRAM devices of the invention have a read/write speed of a conventional SRAM and non-volatile property of a non-volatile memory cell. The methods of operations for the NVSRAM devices of the invention are also disclosed.

Abstract: Field Side Sub-bitline NOR-type (FSNOR) flash array and the methods of fabrication are disclosed. The field side sub-bitlines of the invention formed with the same impurity type as the memory cells' source/drain electrodes along the two sides of field trench oxide link all the source electrodes together and all the drain electrodes together, respectively, for a string of semiconductor Non-Volatile Memory (NVM) cells in a NOR-type flash array of the invention. Each field side sub-bitline is connected to a main metal bitline through a contact at its twisted point in the middle. Because there are no contacts in between the linked NVM cells' electrodes in the NOR-type flash array of the invention, the wordline pitch and the bitline pitch can be applied to the minimum geometrical feature of a specific technology node. The NOR-type flash array of the invention provides at least as high as those in the conventional NAND flash array in cell area density.

Abstract: The present invention provides a stirring mechanism with magnetic force. It has a central rotary arm with permanent magnet, as well as a plurality of lever arms, each having one respective permanent magnet. A track disk rotates synchronously with the central rotary arm. An elliptic track slot in the track disk traps the lever arms to swing forward and backward. The lever arms exhibit alternate motions of approaching and leaving, thereby causing a stirring effect.

Abstract: An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor device and the substrate. Discrete conductive elements are placed between the outer peripheral portion of the second semiconductor device and a second surface of the substrate. Intermediate portions of the discrete conductive elements pass outside of a side surface of the substrate. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed.

Abstract: The present invention provides a method of making pure white light source. A phosphor powder which at least comprises three elements Zn, Se, and O is used for being excited by a purple-LED to emit pure red light (650 nm). The phosphor powder is coated on the purple-LED (Ex. chromaticity coordinate of x:0.26, y:0.10), and then placed aside a pure green-LED (or chip), when the purple-LED and the green-LED are electrified, a pure white light source with high color rendering index and high color saturation is obtained.