Abstract: In an example, a target material is immobilized on two opposed sequencing surfaces of a flow cell using first and second fluids. The first fluid has a density less than a target material density and the second fluid has a density greater than the target material density; or the second fluid has a density less than the target material density and the first fluid has a density greater than the target material density. The first fluid (including the target material) is introduced into the flow cell, whereby at least some of the target material becomes immobilized by capture sites on one of the sequencing surfaces. The first fluid and non-immobilized target material are removed. The second fluid (including target material) is introduced into the flow cell, whereby at least some of the target material becomes immobilized by capture sites on another of the sequencing surfaces.

Abstract: The Non-Volatile Arithmetic Memory Operator (NV-AMO) including a non-volatile memory cell for storing non-volatile data and a first input terminal for receiving volatile variable data is applied to perform the arithmetic operations over the volatile variable data and the non-volatile data. The NV-AMO can also be configured multiple-times for new computations. The constructions of NV-AMO in Arithmetic Logic Units (ALU) can be applied in DSP (Digital Signal Processor) computations and DNN (Deep Neural Network) computations.

Abstract: For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.

Abstract: The disclosure relates to methods, compositions, and kits for the identification and analysis of microorganisms in a sample using nucleoside or nucleotide analogs.

Abstract: The multi-digit binary in-memory multiplication devices are disclosed. The multi-digit binary in-memory multiplication devices of the invention can dramatically reduce the operational steps in comparison with the conventional binary multiplier device. In one embodiment with the expense of more hardware, the in-memory multiplication device can achieve one single step operation. Consequently, the multi-digit binary in-memory multiplication device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU), registers, and memory units.

Abstract: The base-2n in-memory adder device mainly comprises Perpetual Digital Perceptron (PDP) in-memory adder with Read Only Memory (ROM) arrays for storing the binary sum codes of the addition table for processing the addition operations of two n-bit binary integer operands. Since the integer numbers can be represented by the binary codes of multiple digits of base-2n integer numbers, the base-2n in-memory adder device can iterate multiple times of the digit-additions to complete the binary code addition for two m-digit base-2n integer operands. Consequently, the base-2n in-memory adder device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU), registers, and memory units.

Abstract: For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.

Abstract: Some embodiments of the methods and compositions provided herein relate to the selective cleavage of a target nucleic acid. Some such embodiments include the selective cleavage of a target nucleic acid that is associated with a DNA-binding protein or comprises a methylated CpG island, with a recombinant nuclease. In some embodiments, the DNA-binding protein comprises a chromatin protein. Some embodiments also include the enrichment of non-target nucleic acids in a sample by selective cleavage of target nucleic acids in the sample, and removal of the cleaved target nucleic acids from the sample.

Abstract: The base-2n in-memory adder device mainly comprises Perpetual Digital Perceptron (PDP) in-memory adder with Read Only Memory (ROM) arrays for storing the binary sum codes of the addition table for processing the addition operations of two n-bit binary integer operands. Since the integer numbers can be represented by the binary codes of multiple digits of base-2n integer numbers, the base-2n in-memory adder device can iterate multiple times of the digit-additions to complete the binary code addition for two m-digit base-2n integer operands. Consequently, the base-2n in-memory adder device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU), registers, and memory units.

Abstract: Embodiments of the methods and compositions provided herein relate to the selective cleavage of target nucleic acids. Some embodiments include recombinase-mediated selective cleavage of target nucleic acids with single-stranded nucleic acid probes and a recombinase. Some embodiments also include the enrichment of non-target nucleic acids in a sample by selective cleavage of target nucleic acids in the sample, and removal of the cleaved target nucleic acids from the sample.

Abstract: An example of a biotin-streptavidin cleavage composition includes a formamide reagent and a salt buffer. The formamide reagent is present in the biotin-streptavidin cleavage composition in an amount ranging from about 10% to about 50%, based on a total volume of the biotin-streptavidin cleavage composition. The salt buffer makes up the balance of the biotin-streptavidin cleavage composition. In some examples, the biotin-streptavidin cleavage composition is used to cleave library fragments from a solid support. In other examples, other mechanisms are used to cleave library fragments from a solid support.

Abstract: An in-memory digital processor, Perpetual Digital Perceptron (PDP), is disclosed. The digital in-memory processor of the invention processes the input digital information according to a database of the digital content data stored/hardwired in the Content Read Only Memory (CROM) array and outputs the correspondent digital response data stored/hardwired in the Response Read Only Memory (RROM) array. The PDP is the hardwired digital in-memory processor without re-configuration capability and similar to the instinct functions of biological hardwired brains without re-shaping their neuromorphic structures from training and learning.

Abstract: A dynamic digital perceptron device is disclosed. The dynamic digital perceptron device of the invention comprises a volatile content memory array, a detection and driver circuit and a volatile response memory array. The dynamic digital perceptron device processes input digital information according to a database of the digital content data stored in the volatile content memory array and outputs the correspondent digital data stored in the volatile response memory array by the detection and driver circuit. Moreover, the volatile content memory array and the volatile response memory array in the dynamic digital perceptron device are constructed by the latch-types of memory cells to handle the rapid and frequent changing digital processing environments.

Abstract: A dynamic digital perceptron device is disclosed. The dynamic digital perceptron device of the invention comprises a volatile content memory array, a detection and driver circuit and a volatile response memory array. The dynamic digital perceptron device processes input digital information according to a database of the digital content data stored in the volatile content memory array and outputs the correspondent digital data stored in the volatile response memory array by the detection and driver circuit. Moreover, the volatile content memory array and the volatile response memory array in the dynamic digital perceptron device are constructed by the latch-types of memory cells to handle the rapid and frequent changing digital processing environments.

Abstract: A wall tile adapted to be molded from materials, including PVC composition material, and comprising: a planar top panel, which comprises an urethane stain shield, a second planar panel which comprises a first Polyvinyl chloride composition, a third planar panel which comprises a composite material having 3D printing on it, a Fourth planar panel which comprises a webbed fiberglass composition, a fifth planar panel which comprises a magnetic substrate, a sixth planar panel which comprises a second Polyvinyl chloride composition, and a seventh panel which comprises a self-adhesive composition.

Abstract: In-memory arithmetic processors for the “n-bit” by “n-bit” multiplication, the “n-bit” by “n-bit” addition, and the “n-bit” by “n-bit” subtraction operations are disclosed. The in-memory arithmetic processors of the invention can obtain the operational resultant integer in the binary format for two inputted integers represented by two “n-bit” binary codes in one-step processing with no sequential multiple-step operations as for the conventional arithmetic binary processors. The in-memory arithmetic processors are implemented by a 2-dimensional memory array with X and Y decoding for the two inputted operational integers in the arithmetic binary operations.

Abstract: The Non-Volatile Arithmetic Memory Operators (NV-AMO) consisting of non-volatile memory devices for storing non-volatile data are applied to perform the arithmetic operations over volatile variable data and the non-volatile data. The NV-AMO can save arithmetic computation power by reducing the data amount fetching from the memory units. The NV-AMO can also be configured multiple-times for new computations. The constructions of NV-AMO in Arithmetic Logic Units (ALU) can be applied in DSP (Digital Signal Processor) computations and DNN (Deep Neural Network) computations.

Abstract: A wall tile adapted to be molded from materials, including PVC composition material, and comprising: a planar top panel, which comprises an urethane stain shield, a second planar panel which comprises a first Polyvinyl chloride composition, a third planar panel which comprises a composite material having 3D printing on it, a Fourth planar panel which comprises a webbed fiberglass composition, a fifth planar panel which comprises a magnetic substrate, a sixth planar panel which comprises a second Polyvinyl chloride composition, and a seventh panel which comprises a self-adhesive composition.

Abstract: A wall tile adapted to be molded from materials, including PVC composition material, and. comprising: a planar top panel, which comprises an urethane stain shield, a second planar panel which comprises a first Polyvinyl chloride composition, a third planar panel which comprises a composite material having 3D printing on it, a Fourth planar panel which comprises a webbed fiberglass composition, a fifth planar panel which comprises a magnetic substrate, a sixth planar panel which comprises a second Polyvinyl chloride composition, and a seventh panel which comprises a self-adhesive composition.

Abstract: For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.