Abstract: A wall tile adapted to be molded from materials, including PVC composition material, and comprising: a planar top panel, which comprises an urethane stain shield, a second planar panel which comprises a first Polyvinyl chloride composition, a third planar panel which comprises a composite material having 3D printing on it, a Fourth planar panel which comprises a webbed fiberglass composition, a fifth planar panel which comprises a magnetic substrate, a sixth planar panel which comprises a second Polyvinyl chloride composition, and a seventh panel which comprises a self-adhesive composition.

Abstract: A wall tile adapted to be molded from materials, including PVC composition material, and comprising: a planar top panel, which comprises an urethane stain shield, a second planar panel which comprises a first Polyvinyl chloride composition, a third planar panel which comprises a composite material having 3D printing on it, a Fourth planar panel which comprises a webbed fiberglass composition, a fifth planar panel which comprises a magnetic substrate, a sixth planar panel which comprises a second Polyvinyl chloride composition, and a seventh panel which comprises a self-adhesive composition.

Abstract: Inspired by the processing methods of biologic brains, we construct a network of multiple configurable non-volatile memory arrays connected with bus-lines as a neuromorphic code processor for code processing. In contrast to the Von-Neumann computing architectures applying the multiple computations for code vector manipulations, the neuromorphic code processor of the invention processes codes according to their configured codes stored in the non-volatile memory arrays. Similar to the brain processor, the neuromorphic code processor applies the one-step feed-forward processing in parallel resulting in a dramatic power reduction compared with the computational methods in the conventional computer processors.

Abstract: Scalable Logic Gate Non-Volatile Memory (LGNVM) NOR-type arrays fabricated by the standard CMOS logic technologies have been applied for the embedded flash solutions in digital circuitries. To significantly reduce the memory array sizes from the previous fabrications, we have applied the topological regularity of memory cells in the arrays and a self-aligned etch process step to eliminate the gate end-caps in the memory areas. Without scarifying the memory array yields, the minimal unit cell size of 12 F2 for the LGNVM NOR flash arrays can be achieved by this method, where F is the minimal feature size for a specific CMOS logic process technology node.

Abstract: A wall tile adapted to be molded from materials, including PVC composition material, and comprising: a planar top panel, which comprises an urethane stain shield, a second planar panel which comprises a first Polyvinyl chloride composition, a third planar panel which comprises a composite material having 3D printing on it, a Fourth planar panel which comprises a webbed fiberglass composition, a fifth planar panel which comprises a magnetic substrate, a sixth planar panel which comprises a second Polyvinyl chloride composition, and a seventh panel which comprises a self-adhesive composition.

Abstract: A non-differential sense amplifier circuit for reading out information in Non-Volatile Memories (NVMs) is disclosed. The circuit comprises a half latch, a PMOSFET device, a switch device and a reset transistor. The PMOSFET device has a source electrode connected to a digital voltage rail, a drain electrode connected to an output node of the half latch and a gate electrode connected to a bitline path coupled with a selected NVM cell. After the bitline path is pre-charged and the reset transistor is turned off, applying a read voltage to a word line related to the selected NVM cell causes a voltage at the gate electrode of the PMOSFET device to drop differently according to an electrical conductance state of the selected NVM cell. The disclosed circuitries can achieve extra low power consumption and high sensing speed compared to those in the conventional sensing scheme.

Abstract: The standby leakage current reduction schemes for digital data storing components are disclosed. By floating the low digital voltage node of the digital data storing components in standby mode, the major standby leakage current paths to the ground voltage caused by the channel diffusion leakage current of MOSFET devices can be terminated. The standby leakage currents will be reduced to the small reverse junction leakage currents to the grounded substrate. For retaining the stored data in the digital data storing components in standby mode, the low digital voltage node is connected to the ground voltage periodically according to a plurality of rectangular voltage pulses outputted from a pulse generator trigged by a low frequency clock oscillator. Due to no external voltage bias to the low digital voltage node other than floating the digital low voltage node, the data recovering process is instant.

Abstract: A recess channel semiconductor non-volatile memory (NVM) device is disclosed. The recess channel MOSFET devices by etching into the silicon substrate for the device channel have been applied to advanced DRAM process nodes. The same etching process of the recess channel MOSFET device is applied to form the recess channel semiconductor NVM device. The tunneling oxides are grown on silicon surface after the recess channel hole etching process. The storing material is deposited into the recess channel holes with coupling dielectrics on top of the storing material. The gate material is then deposited and etched to form the control gate. Owing to the recess channel embedded below the silicon substrate, the scaling challenges such as gate channel length, floating gate interference, high aspect ratio for gate stack etching, and the mechanical stability of gate formation for the semiconductor NVM device can be significantly reduced.

Abstract: The standby leakage current reduction schemes for digital data storing components are disclosed. By floating the low digital voltage node of the digital data storing components in standby mode, the major standby leakage current paths to the ground voltage caused by the channel diffusion leakage current of MOSFET devices can be terminated. The standby leakage currents will be reduced to the small reverse junction leakage currents to the grounded substrate. For retaining the stored data in the digital data storing components in standby mode, the low digital voltage node is connected to the ground voltage periodically according to a plurality of rectangular voltage pulses outputted from a pulse generator trigged by a low frequency clock oscillator. Due to no external voltage bias to the low digital voltage node other than floating the digital low voltage node, the data recovering process is instant.

Abstract: A motor-gearbox assembly includes a housing, a motor, and a gearbox. The housing includes a first alignment mechanism and a second alignment mechanism. The first alignment mechanism is at a first end of the housing and the second alignment mechanism is at a second end of the housing. The motor is mechanically positioned within the housing in accordance with the first alignment mechanism. The gearbox is mechanically positioned within the housing in accordance with the second alignment mechanisms to mechanically couple to the motor.

Abstract: Non-Volatile Static Random Access Memory (NVSRAM) cell devices applying only one single non-volatile element embedded in a conventional Static Random Access Memory (SRAM) cell are disclosed. The NVSRAM cell devices can be integrated into a compact cell array. The NVSRAM devices of the invention have a read/write speed of a conventional SRAM and non-volatile property of a non-volatile memory cell. The methods of operations for the NVSRAM devices of the invention are also disclosed.

Abstract: In view of the neural network information parallel processing, a digital perceptron device analogous to the build-in neural network hardware systems for parallel processing digital signals directly by the processor's memory content and memory perception in one feed-forward step is disclosed. The digital perceptron device of the invention applies the configurable content and perceptive non-volatile memory arrays as the memory processor hardware. The input digital signals are then broadcasted into the non-volatile content memory array for a match to output the digital signals from the perceptive non-volatile memory array as the content-perceptive digital perceptron device.

Abstract: In view of the neural network information parallel processing, a digital perceptron device analogous to the build-in neural network hardware systems for parallel processing digital signals directly by the processor's memory content and memory perception in one feed-forward step is disclosed. The digital perceptron device of the invention applies the configurable content and perceptive non-volatile memory arrays as the memory processor hardware. The input digital signals are then broadcasted into the non-volatile content memory array for a match to output the digital signals from the perceptive non-volatile memory array as the content-perceptive digital perceptron device.

Abstract: A motor-gearbox assembly includes a housing, a motor, and a gearbox. The housing includes a first alignment mechanism and a second alignment mechanism. The first alignment mechanism is at a first end of the housing and the second alignment mechanism is at a second end of the housing. The motor is mechanically positioned within the housing in accordance with the first alignment mechanism. The gearbox is mechanically positioned within the housing in accordance with the second alignment mechanisms to mechanically couple to the motor.

Abstract: A Field Sub-bitline NOR-type (FSNOR) flash array and its operating methods are disclosed. In contrast to the conventional NOR flash array, the FSNOR array is configured in column with multiple 90° rotated NOR pairs linked by field side sub-bitlines to achieve the minimum 4F2 cell size. The FSNOR flash array is divided into multiple sectors by selection transistors for connecting the even/odd sub-bitlines to the global main first metal bitlines. For each FSNOR sector, the two drain electrodes of column-adjacent NOR pairs form the even/odd sub-bitlines separated by trench field oxides respectively, and the common source electrodes of NOR pairs in a column form the common diffusion source lines tied with metal contacts connected to the first metal common source lines. The FSNOR flash array design has enhanced the electrical isolation of the selected NVM cell devices from the unselected NVM cell devices.

Abstract: A Configurable Non-Volatile Content Addressable Memory (CNVCAM) cell consisting of a pair of complementary non-volatile memory devices and a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) is disclosed. The CNVCAM cells can be constructed to form the NOR-type match line memory array and the NAND-type match line memory array. In contrast to the Random Access Memory (RAM) accessed by the address codes with the prior knowledge of memory locations, CNVCAM can be pre-configured into non-volatile memory content data and searched by an input content data to trigger the further computing process. The unique property of CNVCAM can provide a key component for neural computing.

Abstract: A recess channel semiconductor non-volatile memory (NVM) device is disclosed. The recess channel MOSFET devices by etching into the silicon substrate for the device channel have been applied to advanced DRAM process nodes. The same etching process of the recess channel MOSFET device is applied to form the recess channel semiconductor NVM device. The tunneling oxides are grown on silicon surface after the recess channel hole etching process. The storing material is deposited into the recess channel holes with coupling dielectrics on top of the storing material. The gate material is then deposited and etched to form the control gate. Owing to the recess channel embedded below the silicon substrate, the scaling challenges such as gate channel length, floating gate interference, high aspect ratio for gate stack etching, and the mechanical stability of gate formation for the semiconductor NVM device can be significantly reduced.

Abstract: A Configurable Non-Volatile Content Addressable Memory (CNVCAM) cell consisting of a pair of complementary non-volatile memory devices and a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) is disclosed. The CNVCAM cells can be constructed to form the NOR-type match line memory array and the NAND-type match line memory array. In contrast to the Random Access Memory (RAM) accessed by the address codes with the prior knowledge of memory locations, CNVCAM can be pre-configured into non-volatile memory content data and searched by an input content data to trigger the further computing process. The unique property of CNVCAM can provide a key component for neural computing.

Abstract: A Configurable Non-Volatile Content Addressable Memory (CNVCAM) cell consisting of a pair of complementary non-volatile memory devices and a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) is disclosed. The CNVCAM cells can be constructed to form the NOR-type match line memory array and the NAND-type match line memory array. In contrast to the Random Access Memory (RAM) accessed by the address codes with the prior knowledge of memory locations, CNVCAM can be pre-configured into non-volatile memory content data and searched by an input content data to trigger the further computing process. The unique property of CNVCAM can provide a key component for neural computing.

Abstract: A Configurable Non-Volatile Content Addressable Memory (CNVCAM) cell consisting of a pair of complementary non-volatile memory devices and a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) is disclosed. The CNVCAM cells can be constructed to form the NOR-type match line memory array and the NAND-type match line memory array. In contrast to the Random Access Memory (RAM) accessed by the address codes with the prior knowledge of memory locations, CNVCAM can be pre-configured into non-volatile memory content data and searched by an input content data to trigger the further computing process. The unique property of CNVCAM can provide a key component for neural computing.