Abstract: The present disclosure discloses a method for accessing a data visitor directory in a multi-core system, a directory cache device, a multi-core system, and a directory storage unit. The method includes: receiving a first access request sent by a first processor core, where the first access request is used to access an entry, corresponding to a first data block, in a directory; determining, according to the first access request, that a single-pointer entry array has a first single-pointer entry corresponding to the first data block; when determining, according to the first single-pointer entry, that a sharing entry array has a first sharing entry associated with the first single-pointer entry, determining multiple visitors of the first data block according to the first sharing entry. According to embodiments of the present disclosure, storage resources occupied by a directory can be reduced.

Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a semiconductor substrate; forming a first active region, a second active region, a third active region, and a fourth active region in the semiconductor substrate; and forming a middle-voltage P well region (MVPW) in each of the first active region and the second region simultaneously and forming a middle-voltage N well (MVNW) region in each of the third active region and the fourth active region simultaneously.

Abstract: A method and a device for providing a global clock in a system, the terminals in the system are channel connected to each other via paths, each terminal is communicatively connected to a clock source ultimately via a signal recording unit, respectively, the clock source sends a calibration signal to the network, the signal recording unit records the current transmitting time T (0) of the calibration signal, each terminal will receive the calibration signal sequentially due to different distances from the clock source and will return the signal, the backward signals are returned to the signal recording unit along the network sequentially, and the signal recording unit records the time T (n) of each backward signal sequentially, in this way, the signal recording unit can then measure the delay between each terminal and the clock source signal, which can be used as a correction parameter to ensure that all terminals are in exactly the same time reference, in addition, in this way, there is no need to control the

Abstract: A method and a structure for determining a global clock among systems are disclosed. When a standardized time reference is required among systems, a reference clock source may transmit a calibration signal, and a transmitting time Td (0) may be recorded. Each system may respectively record an arrival time Ta (n), transmit a return signal to a signal recording unit of the reference clock source, and record a transmitting time Tb (n), after receiving the calibration signal. Similarly, because of different distances, the signal recording unit may record arrival times Td (n) of the return signals subsequently, and determine time delays Delay (n) between systems and the reference clock source respectively. When all the systems are required to have a completely standardized time reference, a corresponding Delay (n) may be acquired and transmitted to each system.

Abstract: The disclosed subject matter provides an LDMOS device and fabrication method thereof. In an LDMOS device, a drift region and a body region are formed in a substrate. A first trench is formed in the drift region and in the substrate between the drift region and the body region. The first trench is separated from the drift region by a first shallow trench isolation structure. A gate dielectric layer is formed on a side surface and a bottom surface of the first trench. A gate electrode filling up the first trench is formed on the gate dielectric layer with a top surface above a top surface of the semiconductor substrate. A source region is formed in the body region on one side of the gate electrode and a drain region is formed in the drift region on another side of the gate electrode.

Abstract: The present disclosure provides a method for forming a semiconductor device, including: forming a mask layer over a substrate, the mask layer containing an opening, exposing a surface portion of the substrate to form an exposed surface portion of the substrate; forming an insulation structure between the mask layer and the substrate, and in the opening; performing a thinning process on the insulation structure exposed by the opening to form a recess region on a top of the insulation structure; and forming a gate electrode over the insulation structure and covering a portion of the recess region.

Abstract: The organic semiconductor polymers relates to the synthesis of a carbazole-based ladder polymer. The synthesis of the ladder polymer includes forming a precursor conjugated polymer by Suzuki step growth polymerization of 2,7-dibromocarbazole with 1,4-dibromo-2,5-divinylbenzene, followed by end capping with 2-bromostyrene and 2-vinyl-phenylboronic acid. Then, the pendent vinyl groups are closed by ring-closing olefin metathesis to obtain the ladder polymer.

Abstract: Various aspects of the present disclosure are directed to conjugated polymers, their manufacture and their implementations. As may be implemented in connection with one or more embodiments, an apparatus includes a conjugated polymer and a side chain or end chain material connected to the conjugated polymer. The amount and makeup of the side chain or end chain enhance solubility of the resulting modified conjugated polymer, relative to the conjugated polymer itself.

Abstract: The disclosed subject matter provides an LDMOS device and fabrication method thereof. In an LDMOS device, a drift region and a body region are formed in a substrate. A first trench is formed in the drift region and in the substrate between the drift region and the body region. The first trench is separated from the drift region by a first shallow trench isolation structure. A gate dielectric layer is formed on a side surface and a bottom surface of the first trench. A gate electrode filling up the first trench is formed on the gate dielectric layer with a top surface above a top surface of the semiconductor substrate. A source region is formed in the body region on one side of the gate electrode and a drain region is formed in the drift region on another side of the gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate, and a P-well and an N-type drift region disposed in the semiconductor substrate. The P-well includes a lower well region and an upper well region disposed above the lower well region. The lower well region includes a first surface that is near the N-type drift region, and the upper well region includes a second surface that is near the N-type drift region. A distance from the first surface of the lower well region to the N-type drift region is greater than a distance from the second surface of the upper well region to the N-type drift region.

Abstract: A semiconductor device includes a semiconductor substrate, and a P-well and an N-type drift region disposed in the semiconductor substrate. The P-well includes a lower well region and an upper well region disposed above the lower well region. The lower well region includes a first surface that is near the N-type drift region, and the upper well region includes a second surface that is near the N-type drift region. A distance from the first surface of the lower well region to the N-type drift region is greater than a distance from the second surface of the upper well region to the N-type drift region.

Abstract: The present disclosure provides a method for forming a semiconductor device, including: providing a semiconductor substrate; forming a well region and a drift region in the semiconductor substrate; and forming one or more counter-doped regions in the drift region, the one or more counter-doped regions being aligned along a direction vertical to the semiconductor substrate to divide the drift region into a plurality of parts. The semiconductor fabrication method also includes: forming a gate structure on the semiconductor substrate, the gate structure covering a portion of the well region and a portion of the drift region; and forming a source electrode in the well region on one side of the gate structure and a drain electrode in the drift region on another side of the gate structure.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a P-well and an N-well disposed in the semiconductor substrate, a source disposed in the N-well and a drain disposed in the P-well, a shallow trench isolation (STI) structure disposed in the P-well, a gate structure disposed on the semiconductor substrate, wherein a portion of the gate structure extends into the semiconductor substrate and is disposed in a location corresponding to the STI structure.

Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a semiconductor substrate; forming a first active region, a second active region, a third active region, and a fourth active region in the semiconductor substrate; and forming a middle-voltage P well region (MVPW) in each of the first active region and the second region simultaneously and forming a middle-voltage N well (MVNW) region in each of the third active region and the fourth active region simultaneously.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a P-well and an N-well disposed in the semiconductor substrate, a source disposed in the N-well and a drain disposed in the P-well, a shallow trench isolation (STI) structure disposed in the P-well, a gate structure disposed on the semiconductor substrate, wherein a portion of the gate structure extends into the semiconductor substrate and is disposed in a location corresponding to the STI structure.

Abstract: The disclosed subject matter provides an LDMOS device and fabrication method thereof. In an LDMOS device, a drift region and a body region are formed in a substrate. A first trench is formed in the drift region and in the substrate between the drift region and the body region. The first trench is separated from the drift region by a first shallow trench isolation structure. A gate dielectric layer is formed on a side surface and a bottom surface of the first trench. A gate electrode filling up the first trench is formed on the gate dielectric layer with a top surface above a top surface of the semiconductor substrate. A source region is formed in the body region on one side of the gate electrode and a drain region is formed in the drift region on another side of the gate electrode.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, a P-well and an N-well disposed in the semiconductor substrate, a source disposed in the N-well and a drain disposed in the P-well, a shallow trench isolation (STI) structure disposed in the P-well, a gate structure disposed on the semiconductor substrate, wherein a portion of the gate structure extends into the semiconductor substrate and is disposed in a location corresponding to the STI structure.

Abstract: A frictional false twister is disclosed. The twister has a plurality of rotating friction plates located between the nip of the front rollers and the yarn guide. The friction plates are staggeringly arranged for rubbing a twisted yarn. The spinning direction of the twisted yarn is opposite to the rotating direction of the friction plates. Through the action of the frictional false twister, the twist of the yarn between the false twisting device to the front nip can be increased, shortening the twisting triangle height, and increasing the spinning strength. As the yarn and the outer surface of the friction plate make relative sliding and rubbing, the friction damping force correspondingly reduces the spinning tension in the twisting triangle.

Abstract: Filled silicone composition, in situ preparation and use thereof are provided. The composition comprises a mixture of (A) an in situ-prepared treated silica, (B) an in situ-prepared (siloxane-alkylene)-endblocked polydiorganosiloxane, (c) a cure catalyst and (D) a crosslinker. Moreover, the composition can be used as adhesive, coating and sealant.

Abstract: A filament positioning control device for composite spinning of filaments and staple fibers comprises a fixed shaft and a hollow shaft mounted thereon. Left and right spiral wheels with left and right spiral grooves are mounted on the hollow shaft. Left and right positioning plates are provided on outer sides of left and right spiral wheels, each having a guide pin engaged in a spiral groove. Each positioning plate has a guide block engaged in a guide rail. As the hollow shaft is rotated, the spiral wheels rotate accordingly and the guide pins on the left and right positioning wheels move along with the spiral grooves. Because spiral grooves on two spiral wheels have different directions, when the spiral wheels rotate, the distance between positioning grooves on the two positioning plates increases or decreases, thereby changing the distance between two filaments guided by grooves on the positioning plates.