Abstract: A thermal-power power electronic direct-hung energy-storage plant backup power system includes a thermal-power grid connection startup/standby unit, a power electronic energy-storage switching unit and a thermal-power plant unit. The thermal-power grid connection startup/standby unit is connected to the power electronic energy-storage switching unit and the thermal-power plant unit, respectively. The power electronic energy-storage switching unit is connected to the thermal-power plant unit.

Abstract: An automobile seat integrated with height adjustment and angle adjustment comprises a seat body comprising a pedestal skeleton and a backrest skeleton, a height adjustment mechanism comprising a bottom support, a rear connection rod, an upper connection rod and a front connection rod and an angle adjustment mechanism comprising the bottom support, an angle adjustment connection rod, a driving connection rod, a front connection rod and the upper connection rod, the bottom support, the front connection rod and the upper connection rod are common parts of the height adjustment mechanism and the angle adjustment mechanism, the bottom support, the rear connection rod, the upper connection rod and the front connection rod are successively adjacently connected by rotating pairs, and the rear connection rod is connected with a height adjustment driving source which drives the rear connection rod to move when working to realize the height adjustment of the automobile seat.

Abstract: In certain aspects, a memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor coupled to the array of memory cells through at least one of the plurality of bit lines. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode.

Abstract: A multi-objective optimized evaluation method of anti-seismic performance of a slope reinforced by a pile-anchor system is provided. The method includes: training an initial three-dimensional slope numerical calculation model to obtain an target three-dimensional slope numerical calculation model; determining numerical values to be imported into the target three-dimensional slope numerical calculation model according to deformation differences, to obtain a model analysis result; obtaining a simulation operation result according to a reinforcement scheme working condition table of the pile-anchor system; based on the model analysis result and the simulation operation result, evaluating anti-seismic reinforcing performance of the pile-anchor system to obtain comprehensive evaluation values, and then optimizing and evaluating the reinforcement schemes of an overall slope to be reinforced.

Abstract: A memory device includes a stack structure and a channel structure. The stack structure includes interleaved conductive layers and dielectric layers in a first direction. The channel structure extends through the stack structure along the first direction. The channel structure includes a blocking layer, a storage layer, a tunneling layer, and a semiconductor channel stacked along a second direction intersecting the first direction. The dielectric layers extend through the blocking layer, the storage layer, and the tunneling layer along the second direction and are in contact with the semiconductor channel.

Abstract: Structures of a three-dimensional (3D) memory device and systems containing the same are disclosed. In one example, the 3D memory device includes a memory plane, where the memory plane includes a first edge and an array of blocks. The array of blocks includes a plurality of memory blocks configured to store data, where the plurality of memory blocks are separated by continuous slit structures, and a first dummy region between the first edge and the plurality of memory blocks. The first dummy region includes alternating first slit structures and second slit structures, where the first slit structures and the second slit structures are discontinuous slit structures.

Abstract: Disclosed herein is a memory device that includes a stack structure. The stack structure has alternating first layers and dielectric layers. The stack structure has a first surface and a second surface opposite to the first surface. First contact structures include a conductive material. The first contact structures penetrate from the first surface into the stack structure to be in contact respectively with a first portion of first layers. Second contact structures include a conductive material. Each of the second contact structures penetrates from the second surface into the stack structure to be in contact respectively with a remainder portion of conductive layers other than the first portion of the first layers.

Abstract: Embodiments of a three-dimensional (3D) memory device and method for forming the 3D memory device are provided. In an example, the 3D memory device includes a plurality of conductor layers extending over a substrate, a channel structure vertically extending through the conductor layers to the substrate, and a source structure extending through the conductor layers to the substrate. The channel structure may include a blocking layer having a plurality of blocking portions disconnected from one another. Each of the blocking portions may include (i) a vertical blocking portion under a respective conductor layer, and (ii) at least one lateral blocking portion covering a respective lateral surface of the respective conductor layer. The channel structure may also include a memory layer having a plurality of memory portions disconnected from one another, each of the memory portions under and in contact with the respective vertical blocking portion.

Abstract: A three-dimensional (3D) memory device includes a stack structure and a channel structure. The stack structure includes interleaved conductive layers and dielectric layers. The channel structure extends through the stack structure along a first direction. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer. The blocking layer and the storage layer are separated by the dielectric layers into a plurality of sections.

Abstract: A seamless leg rest device for automobile seats comprises a middle fixing bracket, side fixing brackets, link assemblies, a rotary driving assembly, a support plate and a telescopic assembly, wherein a front side of the support plate is covered with a foamed cover assembly, a lower end of the foamed cover assembly stretches across the support plate and is then bent backwards, and a tail end of a bent section of the foamed cover assembly is tensioned on the link assemblies through a telescopic return member. Both the angle and the length of a leg rest can be adjusted, and seams are avoided when the leg rest is adjusted.

Abstract: The present application provides a semiconductor device and a manufacturing method thereof and a memory system. The manufacturing method of the semiconductor device includes: forming a dielectric layer on a stack layer, wherein memory channel structures penetrating through the stack layer along a first direction are disposed in the stack layer, and the first direction is parallel to a stacking direction of the stack layer; forming a plurality of openings penetrating through the dielectric layer along the first direction, with the rest of the dielectric layer forming top selective gate cut lines, wherein the plurality of openings are arranged as being spaced apart along a second direction, one of the top selective gate cut lines is located between two adjacent ones of the openings in the second direction, and the first direction intersects the second direction; and forming a top selective gate layer in the plurality of openings.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof, as well as a memory system. The semiconductor device includes a first semiconductor structure comprising a first well region and transistors in the first well region, and a second semiconductor structure bonded with the first semiconductor structure and including a second well region, and fin field effect transistors in the second well region. Each fin field effect transistor includes a fin structure, a gate oxide layer in contact with a top surface and side surfaces of the fin structure, and a gate layer covering the gate oxide layer.

Abstract: An apparatus for adjusting lying posture in vehicle seats is connected between a lower side of a height adjusting mechanism of the seat and upper sides of upper sliding rails of the seat and comprises an upper fixed bracket, a front end execution mechanism, a front end supporting and driving mechanism and a rear end bracket assembly. The upper fixed bracket is provided with a front end fixed supporting rod, a left end and a right end of which are connected with a left fixed supporting rod and a right fixed supporting rod respectively; inner sides of the left fixed supporting rod and the right fixed supporting rod are connected with a left fixed bracket and a right fixed bracket respectively; and a connecting hole is formed in each of front parts and rear parts of the left fixed supporting rod and the right front end fixed supporting rod.

Abstract: A method and system for determining acoustic emission (AE) parameters of rock based on moment tensor analysis. The method includes: constructing, according to macroscopic mechanical parameters, a numerical model of a rock specimen to be tested; loading the numerical model through particle flow code software to simulate a failure process of the rock specimen to be tested, and identifying fracturing time and positions of microcracks when the PFC software loads the numerical model; determining, when the PFC software loads the numerical model, if rock grains of two sequentially generated microcracks include common rock grains, and an interval for generating the two microcracks is less than duration time of a present AE event, the two microcracks as a same AE event; taking geometric centers of all microcracks within a spatial range of an AE event as source positions of the corresponding AE event; and determining AE parameters of the AE event.

Abstract: The present disclosure relates to a method and system for simulating water-induced rock strength deterioration based on a discrete element method, and relates to the field of simulation of water-induced rock strength deterioration.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a channel structure extending vertically above the substrate and having a plum blossom shape including a plurality of petals in a plan view. The channel structure includes a plurality of semiconductor channels in the plurality of petals, respectively.

Abstract: In certain aspects, a memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor coupled to the array of memory cells through at least one of the plurality of word lines. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a channel structure extending vertically above the substrate and having a plum blossom shape including a plurality of petals in a plan view. The channel structure includes, in each of the plurality of petals, a charge trapping layer, a tunneling layer, a semiconductor channel, and a channel plug. The channel plug is above and in contact with the charge trapping layer, the tunneling layer, and the semiconductor channel.

Abstract: The present disclosure provides a method of processing a semiconductor device having a stack formed over a source sacrificial layer above a substrate, a channel structure extending vertically through the stack and the source sacrificial layer, a gate line cut trench extending vertically through the stack, and a spacer layer covering uncovered top and side surfaces of the stack. The method can include exposing a lower sidewall of the channel structure by removing the source sacrificial layer, forming a protection layer on all uncovered surfaces, exposing a channel layer of the channel structure by removing a first portion of the protection layer and an insulating layer of the channel structure, forming an initial source connection layer over the exposed channel layer, exposing the substrate by removing a second portion of the protection layer, and forming a source connection layer over the initial source connection layer and the exposed substrate.

Abstract: A method of forming a three-dimensional (3D) NAND memory device includes: forming a gate line slit through alternating layers of an oxide layer and a conductive material layer, wherein the conductive material layer is further formed on a sidewall and a bottom of the gate line slit; performing a first etch process to remove portions of the conductive material layer from the sidewall and the bottom of the gate line slit and from between adjacent oxide layers, thereby exposing portions of the oxide layer in the gate line slit; removing the exposed portions of the oxide layer on the sidewall of the gate line slit; and performing a second etch process to remove residues of the conductive material layer in the gate line slit.