Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication method thereof are disclosed. The 3D memory device has an architecture with an increased number of bit lines. In an example, a stack structure is formed above a substrate. A plurality of memory strings each extending vertically through a memory region of the stack structure are formed. A plurality of bit lines are formed over the plurality of memory strings, such that at least one of the plurality of bit lines is electrically connected to a single one of the plurality of memory strings.

Abstract: A detection method and a device based on a laser radar, and a computer readable storage medium are disclosed. The detection method includes: obtaining scanning data of the laser radar (S101); performing algorithm splitting on a feature algorithm for detection based on the scanning data to obtain at least one sub-algorithm capable of parallel processing in the feature algorithm (S102); and performing heterogeneous acceleration for the at least one sub-algorithm to process the scanning data and to obtain a processing result; and obtaining a detected position of an obstacle and a detected drivable area based on the processing result (S103).

Abstract: An optimal design method and system for slope reinforcement with anti-slide piles includes: modeling a slope type to obtain a three-dimensional (3D) slope numerical calculation model; establishing different numerical calculation models for anti-slide piles according to different reinforcement schemes of the anti-slide piles; determining optimization indexes through a coupling analysis of the 3D slope numerical calculation model and the anti-slide pile numerical calculation model; calculating a comprehensive optimization value according to the optimization index; determining an optimal anti-slide pile reinforcement scheme according to the comprehensive optimization value, and determining whether the optimal anti-slide pile reinforcement scheme meets the optimization objective; and carrying out slope reinforcement according to the optimal anti-slide pile reinforcement scheme if yes.

Abstract: The present disclosure provides an optimal design method and system for slope reinforcement with anti-slide piles. The method includes: modeling a slope type to obtain a three-dimensional (3D) slope numerical calculation model; establishing different numerical calculation models for anti-slide piles according to different reinforcement schemes of the anti-slide piles; determining optimization indexes through a coupling analysis of the 3D slope numerical calculation model and the anti-slide pile numerical calculation model; calculating a comprehensive optimization value according to the optimization index; determining an optimal anti-slide pile reinforcement scheme according to the comprehensive optimization value, and determining whether the optimal anti-slide pile reinforcement scheme meets the optimization objective; and carrying out slope reinforcement according to the optimal anti-slide pile reinforcement scheme if yes.

Abstract: A clamp and a shear test device are provided, and relate to the technical field of rock mass mechanics tests. The clamp comprises a box body, wherein an opening is formed in one side of the box body, two clamping structures are oppositely arranged in the box body, a sample is arranged between the two clamping structures, each clamping structure comprises an adjusting mechanism, and a distance between the two clamping structures is adjusted through adjusting mechanisms of the two clamping structures. According to the clamp, real-time dynamic adjustment is conveniently and rapidly achieved, the stability of sample clamping is ensured, and therefore the requirement that the shear load can be truly and effectively transmitted to the sample through the box body is met.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an etch stop layer on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through in the periphery region and in contact with the etch stop layer. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the etch stop layer, and in contact with the at least one first vertical through contact.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an array well structure in a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one vertical through contact in the periphery region and in contact with the array well structure. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the array well structure, and in contact with the at least one vertical through contact.

Abstract: A three-dimensional (3D) memory device includes a memory stack including conductive layers and dielectric layers interleaving the conductive layers, and a channel structure extending through the memory stack along a vertical direction. The channel structure has a plurality of protruding portions protruding along a lateral direction and facing the conductive layers, respectively, and a plurality of normal portions facing the dielectric layers, respectively, without protruding along the lateral direction. The channel structure includes a plurality of blocking structures in the protruding portions, respectively, and a plurality of storage structures in the protruding portions and over the plurality of blocking structures, respectively. A vertical dimension of each of the blocking structures is nominally the same as a vertical dimension of a respective one of the storage structures over the blocking structure.

Abstract: A first opening extending vertically through a dielectric stack is formed above a substrate. The dielectric stack includes vertically interleaved dielectric layers and sacrificial layers. Parts of the sacrificial layers facing the opening are removed to form a plurality of first recesses. A plurality of stop structures are formed along sidewalls of the plurality of first recesses. A plurality of storage structures are formed over the plurality of stop structures in the plurality of first recesses. The plurality of sacrificial layers are removed to expose the plurality of stop structures from a plurality of second recesses opposing the plurality of first recesses. The plurality of stop structures are removed to expose the plurality of storage structures. A plurality of blocking structures are formed over the plurality of storage structures in the plurality of second recesses.

Abstract: The present disclosure relates to a discrete element method (DEM)-based simulation method and system for acoustic emission (AE). The simulation method includes: arranging a monitoring point on a surface of a numerical model; monitoring a velocity waveform of the monitoring point; and analyzing the velocity waveform to obtain a hit, energy, and a b-value of AE. The method in the present disclosure can resolve problems of principle incompliance, poor authenticity, and high occupation of calculation resources in a traditional simulation method for AE.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a channel structure extending vertically above the substrate and having a plum blossom shape including a plurality of petals in a plan view. The channel structure includes, in each of the plurality of petals, a semiconductor channel and a channel plug above and in contact with the semiconductor channel.

Abstract: Aspects of the disclosure provide a semiconductor device and a method for manufacturing the semiconductor device. A channel hole is formed through a stack over a substrate of the semiconductor device. A sidewall of the channel hole extends along a vertical direction perpendicular to the substrate. A gate dielectric structure, a channel layer, and a dielectric structure that extend along the vertical direction are formed in the channel hole. The gate dielectric structure can be formed along the sidewall of the channel hole, and the dielectric structure can be formed over the channel layer. The channel layer can be separated into channel layer sections to form a channel structure that includes the gate dielectric structure and the channel layer sections for respective strings of transistors.

Abstract: A semiconductor device is provided. The semiconductor device includes word line layers and insulating layers that are alternatingly stacked along a vertical direction perpendicular to a substrate of the semiconductor device. The semiconductor device includes a channel structure that extends along the vertical direction through the word line layers and the insulating layers. A cross-section of the channel structure that is perpendicular to the vertical axis includes channel layer sections that are spaced apart from one another.

Abstract: A semiconductor device is provided. The semiconductor device includes word line layers and insulating layers that are alternatingly stacked along a vertical direction perpendicular to a substrate of the semiconductor device. A first channel structure of the semiconductor device extends along a first vertical axis in the vertical direction through the word line layers and the insulating layers. The first channel structure includes a plurality of storage structures and a first isolation structure. The storage structures are arranged around the first isolation structure. The first isolation structure extends along the first vertical axis and separates the storage structures from one another.

Abstract: A three-dimensional (3D) memory device includes a stack structure and a channel structure. The stack structure includes interleaved conductive layers and dielectric layers. The channel structure extends through the stack structure along a first direction. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer. The blocking layer and the storage layer are separated by the dielectric layers into a plurality of sections.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a channel structure extending vertically above the substrate and having a plum blossom shape including a plurality of petals in a plan view. The channel structure includes, in each of the plurality of petals, a charge trapping layer, a tunneling layer, a semiconductor channel, and a channel plug. The channel plug is above and in contact with the charge trapping layer, the tunneling layer, and the semiconductor channel.

Abstract: Embodiments of three-dimensional (3D) semiconductor devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, an isolation structure, and a plurality of capacitor contacts. The memory stack includes vertically interleaved conductive layers and first dielectric layers. The isolation structure extends vertically through at least part of the memory stack to electrically separate the conductive layers into gate electrodes in a core array region and capacitor electrodes in a dummy staircase region. The plurality of capacitor contacts are in contact with at least two of the capacitor electrodes in the dummy staircase region, respectively.

Abstract: Embodiments of three-dimensional (3D) semiconductor devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, an isolation structure, and a plurality of capacitor contacts. The memory stack includes vertically interleaved conductive layers and first dielectric layers. The isolation structure extends vertically through at least part of the memory stack to electrically separate the conductive layers into gate electrodes in a core array region and capacitor electrodes in a dummy staircase region. The plurality of capacitor contacts are in contact with at least two of the capacitor electrodes in the dummy staircase region, respectively.

Abstract: A variable angle loading testing machine is provided, which may include a bottom plate and a base fixedly connected to the bottom plate. A rock-sample accommodating cavity is formed in the base, and a rectangle-shaped sample is suitable for being placed into the rock-sample accommodating cavity. A side of the base is fixedly connected to two arc-shaped tension beams arranged in parallel, and a variable angle loading mechanism is slidably connected between the two arc-shaped tension beams. Through-holes are formed on the base, and an output end of the variable angle loading mechanism abuts against the rectangle-shaped sample through one of the through-holes. Loading and unloading of a stress with variable direction and magnitude under excavation disturbance can be simulated, which is of great significance for understanding mechanical behaviors of rock-soil mass under excavation disturbance.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack disposed on the substrate and including a plurality of interleaved conductive layers and dielectric layers, and a plurality of channel structures each extending vertically through the memory stack and having a plurality of protruding portions abutting the conductive layers and a plurality of normal portions abutting the dielectric layers. Each of the plurality of channel structures includes a blocking layer along a sidewall of the channel structure, and a storage layer over the blocking layer. The storage layer includes a plurality of charge trapping structures in the protruding portions of the channel structure, and a plurality of protecting structures in the normal portions of the channel structure and connecting the plurality of charge trapping structures.