Abstract: An automobile seat integrated with height adjustment and angle adjustment comprises a seat body comprising a pedestal skeleton and a backrest skeleton, a height adjustment mechanism comprising a bottom support, a rear connection rod, an upper connection rod and a front connection rod and an angle adjustment mechanism comprising the bottom support, an angle adjustment connection rod, a driving connection rod, a front connection rod and the upper connection rod, the bottom support, the front connection rod and the upper connection rod are common parts of the height adjustment mechanism and the angle adjustment mechanism, the bottom support, the rear connection rod, the upper connection rod and the front connection rod are successively adjacently connected by rotating pairs, and the rear connection rod is connected with a height adjustment driving source which drives the rear connection rod to move when working to realize the height adjustment of the automobile seat.

Abstract: An apparatus for adjusting lying posture in vehicle seats is connected between a lower side of a height adjusting mechanism of the seat and upper sides of upper sliding rails of the seat and comprises an upper fixed bracket, a front end execution mechanism, a front end supporting and driving mechanism and a rear end bracket assembly. The upper fixed bracket is provided with a front end fixed supporting rod, a left end and a right end of which are connected with a left fixed supporting rod and a right fixed supporting rod respectively; inner sides of the left fixed supporting rod and the right fixed supporting rod are connected with a left fixed bracket and a right fixed bracket respectively; and a connecting hole is formed in each of front parts and rear parts of the left fixed supporting rod and the right front end fixed supporting rod.

Abstract: Embodiments of semiconductor devices and methods for forming the same are disclosed. In an example, a semiconductor device includes at least one dielectric layer pair including a first dielectric layer and a second dielectric layer different from the first dielectric layer, an interlayer dielectric (ILD) layer in contact with the at least one dielectric layer pair, and one or more capacitors each extending vertically through the ILD layer and in contact with the at least one dielectric layer pair.

Abstract: The disclosure discloses an automobile seat based on an inclined angle adjustment mechanism, including a seat body composed of a cushion skeleton, a backrest skeleton, and a base arranged under the seat body. The upper surface of the base is of a non-plane structure and includes a pedestal located at the lower part and a branch located at the upper part which is integrated or connected by a fixed member, the back of the pedestal is movably connected with the lower part of a third connection rod, the upper part of a seventh connection rod is movably connected with the front of a forth connection rod, and the middle of the seventh connection rod is movably connected with the upper end of the branch, and rotation points are located near the H point of the seat.

Abstract: A method and system for determining acoustic emission (AE) parameters of rock based on moment tensor analysis. The method includes: constructing, according to macroscopic mechanical parameters, a numerical model of a rock specimen to be tested; loading the numerical model through particle flow code software to simulate a failure process of the rock specimen to be tested, and identifying fracturing time and positions of microcracks when the PFC software loads the numerical model; determining, when the PFC software loads the numerical model, if rock grains of two sequentially generated microcracks include common rock grains, and an interval for generating the two microcracks is less than duration time of a present AE event, the two microcracks as a same AE event; taking geometric centers of all microcracks within a spatial range of an AE event as source positions of the corresponding AE event; and determining AE parameters of the AE event.

Abstract: The present disclosure discloses a three-dimensional (3D) memory, which includes a peripheral wafer and an array wafer. The peripheral wafer includes a first peripheral structure and a second peripheral structure. The array wafer includes a substrate, a structure to be tested and multiple interconnecting portions. The substrate includes a first well region and a second well region. The array wafer includes the structure to be tested which has a first connecting portion, a second connecting portion, and multiple interconnecting portions. The first peripheral structure is connected to the first well region and the first connecting portion of the structure to be tested by the first interconnecting portion and the second interconnecting portion respectively. The second peripheral structure is connected to the second well region and the second connecting portion of the structure to be tested by the third interconnecting portion and the fourth interconnecting portion respectively.

Abstract: A method for forming a memory device includes providing an initial semiconductor structure, including a base substrate; a first sacrificial layer formed on the base substrate; a stack structure, disposed on the first sacrificial layer; a plurality of channels, formed through the stack structure and the first sacrificial layer; and a gate-line trench, formed through the stack structure and exposing the first sacrificial layer. The method also includes forming at least one protective layer on the sidewalls of the gate-line trench; removing the first sacrificial layer to expose a portion of each of the plurality of channels and the surfaces of the base substrate, using the at least one protective layer as an etch mask; and forming an epitaxial layer on the exposed surfaces of the base substrate and the plurality of channels.

Abstract: Embodiments of a three-dimensional (3D) memory device and method for forming the 3D memory device are provided. In an example, the 3D memory device includes a plurality of conductor layers extending over a substrate, a channel structure vertically extending through the conductor layers to the substrate, and a source structure extending through the conductor layers to the substrate. The channel structure may include a blocking layer having a plurality of blocking portions disconnected from one another. Each of the blocking portions may include (i) a vertical blocking portion under a respective conductor layer, and (ii) at least one lateral blocking portion covering a respective lateral surface of the respective conductor layer. The channel structure may also include a memory layer having a plurality of memory portions disconnected from one another, each of the memory portions under and in contact with the respective vertical blocking portion.

Abstract: A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The method includes the following steps. An alternating dielectric stack is formed on a substrate. A vertical structure is formed penetrating the alternating dielectric stack in a vertical direction. A bottom dielectric layer of the alternating dielectric stack is removed. An epitaxial layer is formed between the substrate and the alternating dielectric stack after removing the bottom dielectric layer. An insulating layer is formed on the epitaxial layer. The insulating layer is located between the epitaxial layer and the alternating dielectric stack. The influence of the step of forming the vertical structure on the epitaxial layer may be avoided, and defects at the interface between the epitaxial layer and the bottom dielectric layer may be avoided accordingly.

Abstract: In certain aspects, a memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor coupled to the array of memory cells through at least one of the plurality of word lines. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode.

Abstract: In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The gate electrode includes a metal, and the gate dielectric has a thickness between 1.8 nm and 10 nm.

Abstract: In certain aspects, a memory device includes an array of memory cells, a plurality of word lines coupled to the array of memory cells, and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor coupled to the array of memory cells through at least one of the plurality of bit lines. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure including an array of memory cells, a second semiconductor structure including a peripheral circuit, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The peripheral circuit includes a 3D transistor. The array of memory cells is coupled to the peripheral circuit across the bonding interface.

Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication method thereof are disclosed. The 3D memory device has an architecture with an increased number of bit lines. In an example, a stack structure is formed above a substrate. A plurality of memory strings each extending vertically through a memory region of the stack structure are formed. A plurality of bit lines are formed over the plurality of memory strings, such that at least one of the plurality of bit lines is electrically connected to a single one of the plurality of memory strings.

Abstract: A detection method and a device based on a laser radar, and a computer readable storage medium are disclosed. The detection method includes: obtaining scanning data of the laser radar (S101); performing algorithm splitting on a feature algorithm for detection based on the scanning data to obtain at least one sub-algorithm capable of parallel processing in the feature algorithm (S102); and performing heterogeneous acceleration for the at least one sub-algorithm to process the scanning data and to obtain a processing result; and obtaining a detected position of an obstacle and a detected drivable area based on the processing result (S103).

Abstract: An optimal design method and system for slope reinforcement with anti-slide piles includes: modeling a slope type to obtain a three-dimensional (3D) slope numerical calculation model; establishing different numerical calculation models for anti-slide piles according to different reinforcement schemes of the anti-slide piles; determining optimization indexes through a coupling analysis of the 3D slope numerical calculation model and the anti-slide pile numerical calculation model; calculating a comprehensive optimization value according to the optimization index; determining an optimal anti-slide pile reinforcement scheme according to the comprehensive optimization value, and determining whether the optimal anti-slide pile reinforcement scheme meets the optimization objective; and carrying out slope reinforcement according to the optimal anti-slide pile reinforcement scheme if yes.

Abstract: The present disclosure provides an optimal design method and system for slope reinforcement with anti-slide piles. The method includes: modeling a slope type to obtain a three-dimensional (3D) slope numerical calculation model; establishing different numerical calculation models for anti-slide piles according to different reinforcement schemes of the anti-slide piles; determining optimization indexes through a coupling analysis of the 3D slope numerical calculation model and the anti-slide pile numerical calculation model; calculating a comprehensive optimization value according to the optimization index; determining an optimal anti-slide pile reinforcement scheme according to the comprehensive optimization value, and determining whether the optimal anti-slide pile reinforcement scheme meets the optimization objective; and carrying out slope reinforcement according to the optimal anti-slide pile reinforcement scheme if yes.

Abstract: A clamp and a shear test device are provided, and relate to the technical field of rock mass mechanics tests. The clamp comprises a box body, wherein an opening is formed in one side of the box body, two clamping structures are oppositely arranged in the box body, a sample is arranged between the two clamping structures, each clamping structure comprises an adjusting mechanism, and a distance between the two clamping structures is adjusted through adjusting mechanisms of the two clamping structures. According to the clamp, real-time dynamic adjustment is conveniently and rapidly achieved, the stability of sample clamping is ensured, and therefore the requirement that the shear load can be truly and effectively transmitted to the sample through the box body is met.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an etch stop layer on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through in the periphery region and in contact with the etch stop layer. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the etch stop layer, and in contact with the at least one first vertical through contact.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming the array wafer comprises forming an array well structure in a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one vertical through contact in the periphery region and in contact with the array well structure. The method further comprises forming a CMOS wafer, and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the array well structure, and in contact with the at least one vertical through contact.