Abstract: The present disclosure provides anti-CD73 binding molecules, e.g., antibodies and antigen binding fragments thereof. Also provided are pharmaceutical formulations comprising the disclosed compositions, and methods for the diagnosis and treatment of diseases associated with CD73-expression, e.g., cancer. Such diseases can be treated, e.g., by direct therapy with the anti-CD73 binding molecules disclosed herein (e.g., naked antibodies or antibody-drug conjugates that bind CD73), by adjuvant therapy with other antigen-binding anticancer agents such as immune checkpoint inhibitors (e.g., anti-CTLA-4 and anti-PD-1 monoclonal antibodies), and/or by combination therapies where the anti-CD73 molecules are administered before, after, or concurrently with chemotherapy.

Abstract: A pixel structure includes a light emitting diode chip and a light blocking structure. The light emitting diode chip includes a P-type semiconductor layer, an active layer, an N-type semiconductor layer, a first electrode, and K second electrodes. The active layer is located on the P-type semiconductor layer. The N-type semiconductor layer is located on the active layer. The N-type semiconductor layer has a first top surface that is distant from the active layer. The first electrode is electrically connected to the P-type semiconductor layer. The light blocking structure is located in the light emitting diode chip and defines K sub-pixel regions. The active layer and the N-type semiconductor layer are divided into K sub-portions respectively corresponding to the K sub-pixel regions by the light blocking structure. The K sub-pixel regions share the P-type semiconductor layer.

Abstract: Provided are methods, apparatus, and computer-readable mediums for tracking objects that intersect with an exclusion zone defined for a scene being captured by a video camera. An exclusion zone can delineate an area of a video frame where background objects may be moving. The exclusion zone informs an object tracking system that objects within the exclusion zone should not be tracked. In various implementations, the object tracking system can determine that a bounding box for a blob intersects with the exclusion zone. The object tracking system can further, based on the bounding box intersecting with the exclusion zone, prevent outputting of a blob tracker associated with the blob.

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

Abstract: A multiple patterning decomposition method for IC is provided. Features of layout of IC are decomposed into a plurality of nodes. The nodes are classified to assign a plurality of first and second links between the nodes. First and second pseudo colors are assigned to a pair of nodes of each first link. The second links having a pair of nodes both corresponding to the first or second pseudo color are identified. The nodes of the first links are uncolored. A first real color is assigned to the two uncolored nodes of the identified second links in each of the networks. A second real color is assigned to the uncolored nodes connected to the nodes corresponding to the first real color through the first links. First and second masks are formed according to the nodes corresponding to the first and second real colors, respectively.

Abstract: A method of fabricating an integrated circuit (IC) with first and second different lithography techniques includes providing a layout of the IC having IC patterns; and deriving a graph from the layout. The graph has vertices and edges connecting some of the vertices. The vertices represent the IC patterns. The edges are classified into at least two types, a first type connecting two vertices that are to be patterned separately with the first and second lithography techniques, a second type connecting two vertices that are to be patterned in a same process using the first lithography technique or to be patterned separately with the first and second lithography techniques. The method further includes decomposing the vertices into first and second subsets, wherein the IC patterns corresponding to the first and second subsets are to be patterned on a wafer using the first and second lithography techniques respectively.

Abstract: There is provided a luminaire (1) and a collimating optics (2) for LED lights (5). The collimating optics (2) comprises a reflection collimator (3) having a first aperture (7) for allowing incoming light from a LED light (5) to enter the collimator (3) and a second aperture (9) for allowing outgoing light to exit the collimator (3). The reflection collimator (3) further has a wall (15) with a reflective inner surface for guiding the incoming light from the first aperture (7) towards the second aperture (9). A first convex lens (11) is arranged at a distance from the first aperture (7) for refracting the incoming light, and a second convex lens (13) is arranged at the second aperture (9) for refracting and collimating the outgoing light. With the disclosed collimating optics the collimating capability is improved without the size of the optics being increased.

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Abstract: A method of fabricating an integrated circuit (IC) with first and second different lithography techniques includes providing a layout of the IC having IC patterns; and deriving a graph from the layout. The graph has vertices and edges connecting some of the vertices. The vertices represent the IC patterns. The edges are classified into at least two types, a first type connecting two vertices that are to be patterned separately with the first and second lithography techniques, a second type connecting two vertices that are to be patterned in a same process using the first lithography technique or to be patterned separately with the first and second lithography techniques. The method further includes decomposing the vertices into first and second subsets, wherein the IC patterns corresponding to the first and second subsets are to be patterned on a wafer using the first and second lithography techniques respectively.

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.

Abstract: A semiconductor structure may include a first device having first surface with a first bonding layer formed thereon and a second device having a first surface with a second bonding layer formed thereon. The first bonding layer may provide an electrically conductive path to at least one electrical device in the first device. The second bonding layer may provide an electrically conductive path to at least one electrical device in the second device. One of the first or the second devices may include MEMS electrical devices. The first and/or the second bonding layers may be formed of a getter material, which may provide absorption for outgassing.

Abstract: A method of forming a serpentine resistor includes: setting a total length of a schematic resistor to make the schematic resistor to have a first resistance according to a sheet resistance; forming, by using a processor, a serpentine layer corresponding to the schematic resistor, forming, by using the processor, a dummy layer over a portion of the serpentine layer to form a modified serpentine layer, measuring, by using the processor, a modified length of the modified serpentine layer, and comparing, by using the processor, the total length and the modified length to generate a comparison result.

Abstract: The present invention provides a method of additive manufacturing a 3D-printed article, comprising: (a) printing and depositing one or more layers of a slurry by using a 3D printer, wherein the slurry comprises a ceramic powder composition; (b) further injecting an oil around the one or more layers of slurry, wherein the height of the injected oil is lower than the height of the slurry; (c) repeating steps (a) and (b) until a main body with desired geometric shape is obtained; and (d) sintering the main body by heating to obtain the 3D-printed article wherein the temperature of a printing carrier of the 3D printer is from 30 to 80° C.

Abstract: The embodiment of the present invention discloses a method for acquiring an identifier of a terminal in a network. The method includes: acquiring a device identifier of a current terminal which is registered in a network, herein the current terminal is a mobile user; and allocating a corresponding network identifier to the current terminal according to the device identifier of the current terminal such that the current terminal transmits data in the network by using the allocated network identifier, herein, the network identifier is a fixed public network Internet Protocol IP address or a fixed public network IP address and port number segment, allocated to the current terminal. The present invention further discloses a management network element and a computer storage medium.

Abstract: A method of forming a semiconductor device includes forming a conductive feature in a first dielectric layer, forming one or more dielectric layers over the first dielectric layer, and forming a via opening in the one or more dielectric layers, a bottom of the via opening exposing the conductive feature. The method further includes cleaning the via opening using a chemical mixture, and rinsing the via opening using basic-ion doped water after cleaning the via opening.

Abstract: A biological sensing structure includes a mesa integrally connected a portion of a substrate, wherein the mesa has a top surface and a sidewall surface adjacent to the top surface. The biological sensing structure includes a first light reflecting layer over the top surface and the sidewall surface of the mesa. The biological sensing structure includes a filling material surrounding the mesa, wherein the mesa protrudes from the filling material. The biological sensing structure includes a stop layer over the filling material and a portion of the first light reflecting layer. The biological sensing structure includes a second light reflecting layer over a portion of the stop layer and a portion of the top surface of the mesa. The biological sensing structure includes an opening in the second light reflecting layer to partially expose the top surface of the mesa.

Abstract: An electron-beam lithography method includes, computing and outputting a development time of a positive-tone electron-sensitive layer and a parameter recipe of an electron-beam device by using a pattern dimension simulation system, performing a low-temperature treatment to chill a developer solution, utilizing an electron-beam to irradiate an exposure region of the positive-tone electron-sensitive layer based on the parameter recipe, and utilizing the chilled developer solution to develop a development region of the positive-tone electron-sensitive layer based on the development time. The development region is present within the exposure region, and an area of the exposure region is smaller than that of the first portion. As a result, the electron-beam lithography method may control a dimension of a development pattern of the positive-tone electron-sensitive layer more accurately, and may also shrink a minimum dimension of the development pattern of the positive-tone electron-sensitive layer.

Abstract: A valve positioning structure is provided for pressing down a switch arranged in a valve so that fluid is allowed to flow through an inlet opening of the valve when the switch is pressed down in order to control the fluid to flow into/out of at least one bladder. The valve positioning structure includes a casing that receives the valve therein and the casing is provided with a contact member and a manipulation member respectively and movably on upper and lower surfaces of the casing. The contact member and the manipulation member are coupled to each other so that the contact member is operable to drive the manipulation member to move. The manipulation member includes an operation section, where the operation section is movable toward and is enabled to press down the switch when the manipulation member is driven by the contact member to move toward the switch.