Abstract: A method of forming a serpentine resistor includes: setting a total length of a schematic resistor to make the schematic resistor to have a first resistance according to a sheet resistance; forming, by using a processor, a serpentine layer corresponding to the schematic resistor, forming, by using the processor, a dummy layer over a portion of the serpentine layer to form a modified serpentine layer, measuring, by using the processor, a modified length of the modified serpentine layer, and comparing, by using the processor, the total length and the modified length to generate a comparison result.

Abstract: A semiconductor device includes a semiconductor substrate, and a first transistor. The first transistor has a first gate on the semiconductor substrate, and a first lightly doped source/drain region within the semiconductor substrate to determine a first channel region beneath the first gate. A doping ratio determined as a concentration of the first lightly doped source/drain region divided by a concentration of the first channel region ranges from 1.0×1013 to 10×1017.

Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.

Abstract: The present disclosure provides a method of performing optical proximity correction (OPC). An integrated circuit (IC) design layout is received. The design layout contains a plurality of IC layout patterns. Two or more of the plurality of IC layout patterns are grouped together. The grouped IC layout patterns are dissected, or target points are set for the grouped IC layout patterns. Thereafter, an OPC process is performed based on the grouped IC layout patterns.

Abstract: The present disclosure provides anti-CD73 binding molecules, e.g., antibodies and antigen binding fragments thereof. Also provided are pharmaceutical formulations comprising the disclosed compositions, and methods for the diagnosis and treatment of diseases associated with CD73-expression, e.g., cancer. Such diseases can be treated, e.g., by direct therapy with the anti-CD73 binding molecules disclosed herein (e.g., naked antibodies or antibody-drug conjugates that bind CD73), by adjuvant therapy with other antigen-binding anticancer agents such as immune checkpoint inhibitors (e.g., anti-CTLA-4 and anti-PD-1 monoclonal antibodies), and/or by combination therapies where the anti-CD73 molecules are administered before, after, or concurrently with chemotherapy.

Abstract: Disclosed herein are methods and systems for intelligent dual-channel volume adjustment. One embodiment takes the form of a dual-watch mobile radio that includes a first receiver, a second receiver, an audio output port, a one-dimensional (1-D) volume control, and a controller programmed to carry out a set of functions. The set of functions includes receiving first and second audio signals from the first and second receivers, respectively, and generating first and second amplified audio signals at least in part by applying first and second signal gains to the first and second audio signals, respectively, as well as outputting the first and second amplified audio signals via the audio output port. The set of functions also includes receiving volume-control commands from the 1-D volume control, and responsively adjusting the first and second signal gains at least in part by applying a gain function to the first and second signal gains.

Abstract: A multiple patterning decomposition method for IC is provided. Features of layout of IC are decomposed into a plurality of nodes. The nodes are classified to assign a plurality of first and second links between the nodes. First and second pseudo colors are assigned to a pair of nodes of each first link. The second links having a pair of nodes both corresponding to the first or second pseudo color are identified. The nodes of the first links are uncolored. A first real color is assigned to the two uncolored nodes of the identified second links in each of the networks. A second real color is assigned to the uncolored nodes connected to the nodes corresponding to the first real color through the first links. First and second masks are formed according to the nodes corresponding to the first and second real colors, respectively.

Abstract: A semiconductor device and method of manufacture comprise placing an etch stop layer of a material such as aluminum oxide over a conductive element, placing a dielectric layer over the etch stop layer, and placing a hardmask of a material such as titanium nitride over the dielectric layer. Openings are formed to the etch stop layer, the hardmask material is selectively removed, and the openings are then the material of the etch stop layer is then selectively removed to extend the openings through the etch stop layer.

Abstract: An electron-beam lithography method includes, computing and outputting a development time of a positive-tone electron-sensitive layer and a parameter recipe of an electron-beam device by using a pattern dimension simulation system, performing a low-temperature treatment to chill a developer solution, utilizing an electron-beam to irradiate an exposure region of the positive-tone electron-sensitive layer based on the parameter recipe, and utilizing the chilled developer solution to develop a development region of the positive-tone electron-sensitive layer based on the development time. The development region is present within the exposure region, and an area of the exposure region is smaller than that of the first portion. As a result, the electron-beam lithography method may control a dimension of a development pattern of the positive-tone electron-sensitive layer more accurately, and may also shrink a minimum dimension of the development pattern of the positive-tone electron-sensitive layer.

Abstract: The present disclosure relates to a semiconductor device and method of manufacturing the same. The method of manufacturing the semiconductor device includes: providing a substrate, forming a patterned semiconductor layer on the substrate, forming a filter layer to cover the patterned semiconductor layer and forming a low concentration dopant buried layer within the semiconductor substrate, wherein one to forty percent of dopant are filtered out by the filter layer in the formation of the low concentration dopant buried layer.

Abstract: A method for creating a parallax video from a still image includes following steps. Image segmentation is performed for separating at least a foreground object within the still image from an image background of the still image. A blank region of the image background is filled, and the blank region corresponds to where the separated foreground object locates within the still image. A virtual three-dimensional (3D) scene consisting of the foreground object and the image background is created. The virtual 3D scene is analyzed for determining a camera path; and, creating the parallax video by observing the virtual 3D scene with a virtual camera moving along the camera path.

Abstract: A copolymer is provided, which includes a chemical structure of: R is C1-6 alkylene group. T is a terminal group including C1-6 alkyl group, C3-6 cycloalkyl group, or C6-12 aromatic group. l is 0.05 to 0.3, m is 0.1 to 0.2, n is 0.5 to 0.8, l+m+n=1, x is 40 to 100, and o is 10 to 120. An epoxy resin composite is also provided, which includes 100 parts by weight of epoxy resin and 1 to 20 parts by weight of toughness enhancer such as the above copolymer.

Abstract: The present disclosure provides a light emitting structure including a blue light source, a first fluorescent material layer and a second fluorescent material layer. The blue light source has a light emitting surface. The first fluorescent material layer covers the light emitting surface of the blue light source. The first fluorescent material layer consists of a first fluorescent material. An excitation band of the first fluorescent material is in a blue wave band, and an emission band of the first fluorescent material is in a green wave band. The second fluorescent material layer covers the first fluorescent material layer. The second fluorescent material layer consists of a second fluorescent material. An excitation band of the second fluorescent material is in a green wave band, and an emission band of the second fluorescent material is in a red wave band. A light device and a backlight module are also provided herein.

Abstract: The present invention presents an electronic device. The electronic device includes a socket and a supplementary antenna. The socket is disposed on the electronic device, wherein the socket includes an accommodating portion for accommodating an external wireless communication module inserted from the outside. The supplementary antenna is disposed in the electronic device, wherein when the wireless communication module is completely inserted into the accommodating portion, the main antenna of the wireless communication module and the supplementary antenna become electromagnetically coupled; and wherein when the wireless communication module is completely inserted into the accommodating portion, the electronic device transmits/receives wireless signals using the main antenna and the supplementary antenna together.

Abstract: The present disclosure provides anti-CD73 binding molecules, e.g., antibodies and antigen binding fragments thereof. Also provided are pharmaceutical formulations comprising the disclosed compositions, and methods for the diagnosis and treatment of diseases associated with CD73-expression, e.g., cancer. Such diseases can be treated, e.g., by direct therapy with the anti-CD73 binding molecules disclosed herein (e.g., naked antibodies or antibody-drug conjugates that bind CD73), by adjuvant therapy with other antigen-binding anticancer agents such as immune checkpoint inhibitors (e.g., anti-CTLA-4 and anti-PD-1 monoclonal antibodies), and/or by combination therapies where the anti-CD73 molecules are administered before, after, or concurrently with chemotherapy.

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a design layout of the IC, wherein the design layout includes two abutting blocks, the two blocks include target patterns, and the target patterns have different pitches in the two blocks. The method further includes generating mandrel pattern candidates in spaces between adjacent target patterns, and assigning first and second colors to the mandrel pattern candidates according to their priorities. The method further includes removing the mandrel pattern candidates assigned with the second color, and outputting a mandrel pattern in computer-readable format for mask fabrication. The mandrel pattern includes the mandrel pattern candidates that are colored with the first color.

Abstract: A MEMS device is described. The device includes a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, a semiconductor substrate including a second bonding layer, and a cap including a third bonding layer, the cap coupled to the semiconductor substrate by bonding the second bonding layer to the third bonding layer. The first bonding layer includes silicon, the semiconductor substrate is electrically coupled to the MEMS substrate by bonding the first bonding layer to the second bonding layer, and the MEMS substrate is hermetically sealed between the cap and the semiconductor substrate.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. In addition, a sidewall of the gate structure has a top portion having a first inclination, a middle portion having a second inclination, and a bottom portion having a third inclination, and the first inclination, the second inclination, and the third inclination are different from one another.

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a design layout of the IC, wherein the design layout includes two abutting blocks, the two blocks include target patterns, and the target patterns have different pitches in the two blocks. The method further includes generating mandrel pattern candidates in spaces between adjacent target patterns, and assigning first and second colors to the mandrel pattern candidates according to their priorities. The method further includes removing the mandrel pattern candidates assigned with the second color, and outputting a mandrel pattern in computer-readable format for mask fabrication. The mandrel pattern includes the mandrel pattern candidates that are colored with the first color.