Abstract: A phosphor device of an illumination system emitting a first waveband light includes a substrate and a phosphor layer formed on the substrate. The phosphor layer includes a first phosphor agent and a second phosphor agent. The first waveband light is converted into a first color light by the first phosphor agent. The second phosphor agent is distributed over the first phosphor agent and mixed with the first phosphor agent, and the first waveband light is converted into a second color light by the second phosphor agent. The first color light and the second color light are integrated into the second waveband light. The difference between the first wavelength peak of the first color light and the second wavelength peak of the second color light is 50 to 100 nanometers. Therefore, the advantages of increasing the purity, the luminance and the luminous intensity of specific color light are achieved.

Abstract: Disclosed is a method for modifying starch to slow down the digestion rate of modified starch. The present invention utilizes two-stage GBE treatment to convert the long straight-chain starch molecules into highly branched molecules with compact structures so as to decrease the digestion rate of the starch. During the two-stage treatment, granular starch was first treated with GBE, the treated starch was gelatinized in boiling water, and the gelatinized starch was treated with GBE for a second time, leading to an enhanced effect of GBE modification. Compared with the one-staged GBE modification, the two-stage GBE modification can further increase the content of slowly digestible starch in the modified starch and thus decrease the digestion rate of starch.

Abstract: A method of fabricating an integrated circuit (IC) uses a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution. The method includes deriving a graph from an IC layout, the graph having vertices and edges that connect some of the vertices, the vertices representing IC patterns in the IC layout, the edges representing spacing between the IC patterns that are smaller than the second resolution. The method further includes classifying the edges into at least two types, a first type of edges representing spacing that is smaller than the first resolution, a second type of edges representing spacing that is equal to or greater than the first resolution but smaller than the second resolution.

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

Abstract: A hemostatic material, a preparation method thereof, and a pharmaceutical composition containing the same are introduced. The hemostatic material includes 200 to 1600 parts by weight of water-insoluble gelatin and 100 to 1000 parts by weight of hydrating material. The preparation method for the hemostatic material includes the steps of (a) providing 200 to 1600 parts by weight of water-insoluble gelatin and 100 to 1000 parts by weight of hydrating material; and (b) combining the water-insoluble gelatin with the hydrating material to form a hemostatic material. The pharmaceutical composition includes an aforementioned hemostatic material and active pharmaceutical ingredients. Through the aforementioned hemostatic material, hemostatic products can increase the blood absorption capacity.

Abstract: A method of forming a semiconductor device includes forming a conductive feature in a first dielectric layer, forming one or more dielectric layers over the first dielectric layer, and forming a via opening in the one or more dielectric layers, a bottom of the via opening exposing the conductive feature. The method further includes cleaning the via opening using a chemical mixture, and rinsing the via opening using basic-ion doped water after cleaning the via opening.

Abstract: A lower grille assembly preventing light leakage and fixedly connected to a bumper skin of a vehicle and comprising a lower grille body with a buckle mounting orifice and a lower grille trim with a buckle, wherein the lower grille trim is fixedly connected to the lower grille body by means of the buckle and the buckle mounting orifice; a buckle flange extending outward on the buckle of the lower grille trim, the buckle including a U-shaped groove for receiving an end of the skin and in a clearance fit with the end, so as to clamp and support the skin, effectively ensuring a Z-direction clearance between the trim and the skin, preventing the skin from falling due to its dead weight, and avoiding light leakage due to an increased Z-direction clearance between the skin and the lower grille assembly resulting from deformation of the lower grille assembly.

Abstract: A display panel and manufacturing method thereof and a display device are provided. The display panel includes: a base substrate, a light-emitting layer located on the base substrate, and a beam diffusion layer located on the side of a light-emergent surface of the light-emitting layer. The light-emitting layer includes a plurality of pixel units arranged in an array; and the beam diffusion layer includes a beam diffusion element corresponding to at least one of the pixel units, which is used to expand a light-emergent beam of the corresponding pixel unit. The beam diffusion element may expand the light-emergent beam of the corresponding pixel unit, which increases the area of the light-emergent surface of the pixel unit. Thus, the number of pixel units provided in a large-sized display panel may be reduced, the power consumption thereof may be decreased, and the occurrence of burn-in inside the display panel may be avoided.

Abstract: Disclosed is a method for modifying starch to slow down the digestion rate of modified starch. The present invention utilizes two-stage GBE treatment to convert the long straight-chain starch molecules into highly branched molecules with compact structures so as to decrease the digestion rate of the starch. During the two-stage treatment, granular starch was first treated with GBE, the treated starch was gelatinized in boiling water, and the gelatinized starch was treated with GBE for a second time, leading to an enhanced effect of GBE modification. Compared with the one-staged GBE modification, the two-stage GBE modification can further increase the content of slowly digestible starch in the modified starch and thus decrease the digestion rate of starch.

Abstract: An optical inspection system includes at least one lighting module, a plurality of image-sensing units, and an editing and computing unit. Each lighting module is configured to generate a light beam for illuminating an object; each image-sensing unit is configured to capture an inspecting image of the object, wherein two adjacent inspecting images of the object has a repeated image; the editing and computing unit receiving the inspecting images captured by the image-sensing unit is configured to position the inspecting images in accordance with the repeated images and then recombinant the inspecting images for creating a full inspecting image.

Abstract: A semiconductor device includes a substrate, a channel layer, an active layer, and a gate electrode. The channel layer has a fin portion over the substrate. The active layer is over at least the fin portion of the channel layer. The active layer is configured to cause a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer. The gate electrode is in contact with a sidewall of the fin portion of the channel layer.

Abstract: A server and a number of client devices are connected via a network. Interactive objects are initiated in one of the client devices and delivered to any number of other client devices over the network. Real-time interactions between the object sender and the object receiver(s) can then be engaged using event-triggering mechanisms built into the client devices and applied onto the objects, and be coordinated by a coordinating module in the server. The interactive objects may carry instructions for event-triggered loading, activating and execution of functional widgets, such as workflows or collaborations, stored in the same server or elsewhere on the network. Once loaded in a client device, a widget needs not to be reloaded upon further use. Furthermore, the coordinating module may be linked to a machine-learning module in the same server or elsewhere on the network.

Abstract: The present disclosure provides anti-CD73 binding molecules, e.g., antibodies and antigen binding fragments thereof. Also provided are pharmaceutical formulations comprising the disclosed compositions, and methods for the diagnosis and treatment of diseases associated with CD73-expression, e.g., cancer. Such diseases can be treated, e.g., by direct therapy with the anti-CD73 binding molecules disclosed herein (e.g., naked antibodies or antibody-drug conjugates that bind CD73), by adjuvant therapy with other antigen-binding anticancer agents such as immune checkpoint inhibitors (e.g., anti-CTLA-4 and anti-PD-1 monoclonal antibodies), and/or by combination therapies where the anti-CD73 molecules are administered before, after, or concurrently with chemotherapy.

Abstract: A pixel structure includes a light emitting diode chip and a light blocking structure. The light emitting diode chip includes a P-type semiconductor layer, an active layer, an N-type semiconductor layer, a first electrode, and K second electrodes. The active layer is located on the P-type semiconductor layer. The N-type semiconductor layer is located on the active layer. The N-type semiconductor layer has a first top surface that is distant from the active layer. The first electrode is electrically connected to the P-type semiconductor layer. The light blocking structure is located in the light emitting diode chip and defines K sub-pixel regions. The active layer and the N-type semiconductor layer are divided into K sub-portions respectively corresponding to the K sub-pixel regions by the light blocking structure. The K sub-pixel regions share the P-type semiconductor layer.

Abstract: Provided are methods, apparatus, and computer-readable mediums for tracking objects that intersect with an exclusion zone defined for a scene being captured by a video camera. An exclusion zone can delineate an area of a video frame where background objects may be moving. The exclusion zone informs an object tracking system that objects within the exclusion zone should not be tracked. In various implementations, the object tracking system can determine that a bounding box for a blob intersects with the exclusion zone. The object tracking system can further, based on the bounding box intersecting with the exclusion zone, prevent outputting of a blob tracker associated with the blob.

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

Abstract: A multiple patterning decomposition method for IC is provided. Features of layout of IC are decomposed into a plurality of nodes. The nodes are classified to assign a plurality of first and second links between the nodes. First and second pseudo colors are assigned to a pair of nodes of each first link. The second links having a pair of nodes both corresponding to the first or second pseudo color are identified. The nodes of the first links are uncolored. A first real color is assigned to the two uncolored nodes of the identified second links in each of the networks. A second real color is assigned to the uncolored nodes connected to the nodes corresponding to the first real color through the first links. First and second masks are formed according to the nodes corresponding to the first and second real colors, respectively.

Abstract: A method of fabricating an integrated circuit (IC) with first and second different lithography techniques includes providing a layout of the IC having IC patterns; and deriving a graph from the layout. The graph has vertices and edges connecting some of the vertices. The vertices represent the IC patterns. The edges are classified into at least two types, a first type connecting two vertices that are to be patterned separately with the first and second lithography techniques, a second type connecting two vertices that are to be patterned in a same process using the first lithography technique or to be patterned separately with the first and second lithography techniques. The method further includes decomposing the vertices into first and second subsets, wherein the IC patterns corresponding to the first and second subsets are to be patterned on a wafer using the first and second lithography techniques respectively.

Abstract: There is provided a luminaire (1) and a collimating optics (2) for LED lights (5). The collimating optics (2) comprises a reflection collimator (3) having a first aperture (7) for allowing incoming light from a LED light (5) to enter the collimator (3) and a second aperture (9) for allowing outgoing light to exit the collimator (3). The reflection collimator (3) further has a wall (15) with a reflective inner surface for guiding the incoming light from the first aperture (7) towards the second aperture (9). A first convex lens (11) is arranged at a distance from the first aperture (7) for refracting the incoming light, and a second convex lens (13) is arranged at the second aperture (9) for refracting and collimating the outgoing light. With the disclosed collimating optics the collimating capability is improved without the size of the optics being increased.