Abstract: The present invention provides a method of additive manufacturing a 3D-printed article, comprising: (a) printing and depositing one or more layers of a slurry by using a 3D printer, wherein the slurry comprises a ceramic powder composition; (b) further injecting an oil around the one or more layers of slurry, wherein the height of the injected oil is lower than the height of the slurry; (c) repeating steps (a) and (b) until a main body with desired geometric shape is obtained; and (d) sintering the main body by heating to obtain the 3D-printed article wherein the temperature of a printing carrier of the 3D printer is from 30 to 80° C.

Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.

Abstract: Voltage reference circuits are provided. A voltage reference circuit includes a transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit and an output node. The gate and the drain of the flipped-gate transistor are coupled to the gate and the drain of the transistor. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and the mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the transistor in response to the mirroring current. The output node is coupled to the source of the transistor and the second current mirror unit, and is configured to output a reference voltage.

Abstract: The present disclosure discloses a pH-sensitive starch-based microcapsule encapsulating a fat-soluble substance and a preparation method thereof, and belongs to the field of preparation of starch-based hydrogel microcapsules. The method of the present disclosure comprises performing acid hydrolysis on starch to obtain acid-hydrolyzed carboxymethyl starch, mixing the acid-hydrolyzed carboxymethyl starch with xanthan gum to obtain a compounded solution of starch and colloid, adding an emulsifier and the fat-soluble substance, emulsifying to obtain an emulsion, and drying to obtain the microcapsule.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

Abstract: A method performed by an electronic device is described. The method includes receiving an image. The image depicts a face. The method also includes detecting at least one facial landmark of the face in the image. The method further includes receiving a depth image of the face and determining at least one landmark depth by mapping the at least one facial landmark to the depth image. The method also includes determining a plurality of scales of depth image pixels based on the at least one landmark depth and determining a scale smoothness measure for each of the plurality of scales of depth image pixels. The method additionally includes determining facial liveness based on at least two of the scale smoothness measures. Determining the facial liveness may be based on a depth-adaptive smoothness threshold and/or may be based on a natural face size criterion.

Abstract: A smart home includes Internet of things (IOT) devices that are paired with an IOT gateway. A backend system is in communication with the IOT gateway to receive IOT operating data of the IOT devices. The backend system generates a machine learning model for an IOT device. The machine learning model is consulted with IOT operating data of the IOT device to detect anomalous operating behavior of the IOT device. The machine learning model is updated as more and newer IOT operating data of the IOT device are received by the backend system.

Abstract: A pixel structure includes a light emitting diode chip and a light blocking structure. The light emitting diode chip includes a P-type semiconductor layer, an active layer, an N-type semiconductor layer, a first electrode, and K second electrodes. The active layer is located on the P-type semiconductor layer. The N-type semiconductor layer is located on the active layer. The N-type semiconductor layer has a first top surface that is distant from the active layer. The first electrode is electrically connected to the P-type semiconductor layer. The light blocking structure is located in the light emitting diode chip and defines K sub-pixel regions. The active layer and the N-type semiconductor layer are divided into K sub-portions respectively corresponding to the K sub-pixel regions by the light blocking structure. The K sub-pixel regions share the P-type semiconductor layer.

Abstract: A support fixture is adapted for utilization of a test probe, and includes two pedestals and at least one moveable carriage assembly. Each pedestal includes a spacing block and at least one side plate connected to the spacing block extending in a longitudinal direction. The at least one moveable carriage includes a vertical panel and an adjustable holding device. The vertical panel is engaged with the at least one side plate of one of the two pedestals, and is slidable parallel to the longitudinal direction relative to the at least one side plate of each of the two pedestals. The adjustable holding device is operable for fixing the vertical panel to the at least one side plate of the one of the two pedestals and is adapted to hold the test probe.

Abstract: A system and method of instant-messaging bot that provide a chatbot and human agents working in accord in communicating with users over a public instant-messaging (IM) platform includes a chatbot application and an IM platform, both built for an enterprise. The enterprise IM platform is connected to the chatbot application and separately connected to one or more public IM platforms via the Internet. The chatbot application contains software for receiving, processing, analyzing and responding to human-generated messages in a human-like manner. The enterprise IM platform contains software for managing traffic of IM messages exchanged among the chatbot, one or more human agents connected to the enterprise IM platform, and any user connected to one of the public IM platforms.

Abstract: Systems and methods of instant-messaging bot for robotic process automation (RPA) and robotic textual-content extraction from digital images include a chatbot application, a software RPA manager, and an instant-messaging (IM) platform, all built for an enterprise. The enterprise IM platform is connected to one or more public IM platforms over the Internet. The RPA manager contains multiple modules of enterprise workflows and receives instructions from the enterprise chatbot for executing individual workflows. The system allows enterprise users connected to the enterprise IM platform, and external users connected to the public IM platforms, to use instant messaging to initiate enterprise workflows that are automated with the help of the enterprise chatbot and delivered via instant messaging. Furthermore, textual-content extraction from digital images is incorporated in the RPA manager as an enterprise workflow, and provides improved convolutional neural network (CNN) methods for textual-content extraction.

Abstract: The embodiments of the resent disclosure provide a display pane, a manufacturing method thereof, and a display device. The display panel includes a first substrate and a second substrate cell-assembled to each other, a light emitting member layer disposed between the first substrate and the second substrate and a light diffusion layer disposed on a light exiting side of the light emitting member layer, the light emitting member layer includes a plurality of light emitting units and imaging holes disposed on at least two sides of each of the light emitting units, the light diffusion layer includes a reflective member configured to reflect a light ray emitted by the light emitting unit and reaching the reflective member, and the reflected light ray reflected by the reflective member exits from the imaging holes.

Abstract: A hemostatic material, a preparation method thereof, and a pharmaceutical composition containing the same are introduced. The hemostatic material includes 200 to 1600 parts by weight of water-insoluble gelatin and 100 to 1000 parts by weight of hydrating material. The preparation method for the hemostatic material includes the steps of (a) providing 200 to 1600 parts by weight of water-insoluble gelatin and 100 to 1000 parts by weight of hydrating material; and (b) combining the water-insoluble gelatin with the hydrating material to form a hemostatic material. The pharmaceutical composition includes an aforementioned hemostatic material and active pharmaceutical ingredients. Through the aforementioned hemostatic material, hemostatic products can increase the blood absorption capacity.

Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.

Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

Abstract: A semiconductor device includes a semiconductor substrate, and a first transistor. The first transistor has a first gate on the semiconductor substrate, and a first lightly doped source/drain region within the semiconductor substrate to determine a first channel region beneath the first gate. A doping ratio determined as a concentration of the first lightly doped source/drain region divided by a concentration of the first channel region ranges from 1.0×1013 to 1.0×1017.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.