Abstract: A data storage infrastructure may establish a partition that includes a first data center and a second data center that is geographically separated from the first data center. The data storage infrastructure may replicate a full snapshot and one or more incremental snapshots of a virtual machine from a first data management platform to a second data management platform, where the virtual machine is migrated from a first host of the first host group to a second host of the second host group upon a failover event occurring at the first data center. The data storage infrastructure may then capture an incremental snapshot of the virtual machine based on linking a first instance of the virtual machine that was replicated from the first data management platform and a second instance of the virtual machine that is managed by the second data management platform.

Abstract: An in-place data recovery method and system include receiving a user request to restore a virtual machine to a version corresponding to a first point in time, identifying a first snapshot of the virtual machine based on the user request, generating a second snapshot of the virtual machine, identifying a second data block in the second snapshot that includes modified data derived from data content of a first data block in the first snapshot, generating reverse incremental backup data including the first data block, and restoring the virtual machine in-place based on the reverse incremental backup data.

Abstract: A method for modelling timing behavior using augmented sensitivity data for physical parameters is disclosed. The method includes acquiring timing library data and sensitivity data for a physical parameter associated with a circuit design, generating a timing behavior model for the circuit design based on the timing library data and sensitivity data for the physical parameter, and storing the timing behavior model. The timing behavior model reduces a difference between a current known best measurement associated with the circuit design and a static timing analysis timing for the circuit design.

Abstract: A data management system comprises: a storage appliance configured to store a snapshot of a virtual machine; and one or more processors in communication with the storage appliance. The one or more processors are configured to perform operations including: identifying a plurality of shards of the virtual machine; requesting a snapshot of each of the plurality of shards; receiving the shards asynchronously; ordering the received snapshot shards sequentially into a results queue; and storing a single snapshot of the virtual machine based on the ordered snapshot shards. Operations may further include maintaining a flow control queue that limits the number of snapshot shards requested.

Abstract: The present disclosure provides a direct current (DC) transformer error detection apparatus for a pulsating harmonic signal, including a DC and pulsating harmonic current output module and an external detected input module, where the DC and pulsating harmonic current output module outputs a DC and a DC superimposed pulsating harmonic current to an internal sampling circuit and a self-calibrated standard resistor array; and the internal sampling circuit converts the input DC and the input DC superimposed pulsating harmonic current into a voltage signal, and sends the voltage signal to an analog-to-digital (AD) sampling and measurement component through a front-end conditioning circuit and a detected input channel. The DC transformer error detection apparatus can complete self-calibration for measurement of the DC and the pulsating harmonic signal on a test site.

Abstract: Disclosed is a control method for an audio device, the audio device includes a wireless charging module and a display screen, and the control method for the audio device includes the following steps: in response to detecting a mobile device is placed on the audio device, acquiring a screen placement state of the mobile device, the screen placement state includes at least one of a screen flat state, a screen horizontal state and a screen vertical state; and displaying display content of the display screen on a screen of the mobile device according to the screen placement state. This disclosure further provides an audio device and a computer-readable storage medium. The problem that the display effect of the display screen of the audio device will be affected when the audio device performs wireless charging for the mobile device has been solved.

Abstract: A data storage infrastructure may establish a partition that includes a first data center and a second data center that is geographically separated from the first data center. The data storage infrastructure may replicate a full snapshot and one or more incremental snapshots of a virtual machine from a first data management platform to a second data management platform, where the virtual machine is migrated from a first host of the first host group to a second host of the second host group upon a failover event occurring at the first data center. The data storage infrastructure may then capture an incremental snapshot of the virtual machine based on linking a first instance of the virtual machine that was replicated from the first data management platform and a second instance of the virtual machine that is managed by the second data management platform.

Abstract: This application provides a biphenyl diaryl pyrimidine derivative with an aromatic heterocyclic structure, a pharmaceutically-acceptable salt, a stereoisomer, a hydrate and a solvate thereof, where the biphenyl diaryl pyrimidine derivative is shown in formula (I). This application also provides a pharmaceutical composition containing the biphenyl diaryl pyrimidine derivative, or a pharmaceutically-acceptable salt, a stereoisomer, a hydrate and a solvate thereof, and a pharmaceutically-acceptable carrier. This application further provides a method of treating AIDS by administering a therapeutically effective amount of the pharmaceutical composition to a patient in need.

Abstract: A data backup and recovery method and system using allocated data blocks include identifying a first snapshot associated with a virtual machine; accessing changed block tracking data associated with data changes occurred in the virtual machine, the data changes corresponding to a set of changed data blocks; accessing block allocation status data associated with the set of changed data blocks; identifying one or more allocated data blocks from the set of changed data blocks that are associated with allocated status based on the block allocation status data; and storing the one or more allocated data blocks to a storage device.

Abstract: Method and an apparatus are provided for indicating a fault status. The method includes: a first device determines N alignment marker AM groups, where the N AM groups include first indication information, the first indication information is used to indicate a fault status of R receiving logical lanes of the first device, and each of the N AM groups includes M pieces of alignment marker group lane AMGL information; and in an ith period of N periods, the first device respectively sends M pieces of AMGL information constituting an ith AM group to a second device over M transmitting logical lanes.

Abstract: For each circuit element in a pair of launch and capture paths, a parameter value of the circuit element may be modified by a variation amount that is assigned to a class of circuit elements to which the circuit element belongs. Next, a timing slack may be computed for the pair of launch and capture paths.

Abstract: A forecasting modeling computing system includes a processors and a memory including a set of computer-executable instructions that, when executed by the processor, cause the forecasting modeling computing system to receive design parameters, determine a predicted median particle size, identify a predictive quadratic model, and display a response surface visualization. A computer-implemented method includes receiving design parameters, determining a predicted median particle size, identifying a predictive quadratic model; and display a response surface visualization.

Abstract: The present invention discloses a compound fluorine-free foam extinguishing agent and a preparation method therefor, comprising components of the following parts by weight: 6-8 parts of alkyl glycoside, 10-14 parts of polysiloxane quaternary ammonium salt, 0.5-1 part of silicon dioxide and 60-65 parts of water. The compound fluorine-free foam extinguishing agent prepared by the present invention has a high stability, a high expansion, an obvious fire extinguishing effect and a higher environment-friendliness. The polysiloxane quaternary ammonium salt contains hydrophobic polysiloxane long chains, has a high temperature resistance, and collaborates with the alkyl glycoside to be adsorbed on the surface of silicon dioxide particles, which improves the stability of the silicon dioxide in a solution and reduces the surface tension of the solution.

Abstract: An in-place data recovery method and system include receiving a user request to restore a virtual machine to a version corresponding to a first point in time, identifying a first snapshot of the virtual machine based on the user request, generating a second snapshot of the virtual machine, identifying a second data block in the second snapshot that includes modified data derived from data content of a first data block in the first snapshot, generating reverse incremental backup data including the first data block, and restoring the virtual machine in-place based on the reverse incremental backup data.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes an anti-fuse unit, and the anti-fuse unit includes a selection unit and a memory cell. The semiconductor structure further includes: a substrate; a gate provided in the substrate, where in a cross section perpendicular to the substrate, the gate includes a first sidewall and a second sidewall opposite to each other; a first doped region, provided in the substrate and close to the first sidewall; a second doped region, provided in the substrate and close to the second sidewall; and an oxide layer, covering a partial surface of the gate. The gate, the first doped region and the oxide layer form the memory cell; the gate, the first doped region, the second doped region, and the oxide layer form the selection unit.

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, and an electronic device, which relate to the field of semiconductor device test technologies. The control chip includes a built-in self-test BIST circuit. The method is performed by the BIST circuit. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, an electronic device, relating to the field of semiconductor device test technology. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, a memory chip can be used for storing test vectors for a control chip, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

Abstract: A memory test method includes: testing a first memory to acquire defect information of the first memory; acquiring repair information of the first memory according to the defect information of the first memory; and storing the repair information of the first memory in a second memory. In the technical solutions provided in the embodiments of the present disclosure, other memories may be used to store the repair information of the currently tested memory, so that the storage space can be increased and the test efficiency can be improved.

Abstract: Disclosed are an online analysis system and method for a line loss of a transmission line. The system includes: a terminal extension and a terminal host, where time information synchronization between the terminal extension and the terminal host and between terminal extensions is performed by a clock synchronization module, and communication between the terminal extension and the terminal host and between the terminal extensions is performed by a communications module; and a line loss management platform, configured to receive measurement data of the terminal extension and the terminal host, match time information in the measurement data, and if time information in the measurement data of the terminal extension and the terminal host is matched, and time information in measurement data of the terminal extensions is matched, determine corresponding line loss information based on corresponding measurement information.

Abstract: Method and an apparatus are provided for indicating a fault status. The method includes: a first device determines N alignment marker AM groups, where the N AM groups include first indication information, the first indication information is used to indicate a fault status of R receiving logical lanes of the first device, and each of the N AM groups includes M pieces of alignment marker group lane AMGL information; and in an ith period of N periods, the first device respectively sends M pieces of AMGL information constituting an ith AM group to a second device over M transmitting logical lanes.