Abstract: Example embodiments relate generally to systems and methods for continuous data protection (CDP) and more specifically to an input and output (I/O) filtering framework and log management system to seek a near-zero recovery point objective (RPO).

Abstract: Disclosed are an online analysis system and method for a line loss of a transmission line. The system includes: a terminal extension and a terminal host, where time information synchronization between the terminal extension and the terminal host and between terminal extensions is performed by a clock synchronization module, and communication between the terminal extension and the terminal host and between the terminal extensions is performed by a communications module; and a line loss management platform, configured to receive measurement data of the terminal extension and the terminal host, match time information in the measurement data, and if time information in the measurement data of the terminal extension and the terminal host is matched, and time information in measurement data of the terminal extensions is matched, determine corresponding line loss information based on corresponding measurement information.

Abstract: A memory test method includes: testing a first memory to acquire defect information of the first memory; acquiring repair information of the first memory according to the defect information of the first memory; and storing the repair information of the first memory in a second memory. In the technical solutions provided in the embodiments of the present disclosure, other memories may be used to store the repair information of the currently tested memory, so that the storage space can be increased and the test efficiency can be improved.

Abstract: A data management system comprises: a storage appliance configured to store a snapshot of a virtual machine; and one or more processors in communication with the storage appliance. The one or more processors are configured to perform operations including: identifying a plurality of shards of the virtual machine; requesting a snapshot of each of the plurality of shards; receiving the shards asynchronously; ordering the received snapshot shards sequentially into a results queue; and storing a single snapshot of the virtual machine based on the ordered snapshot shards. Operations may further include maintaining a flow control queue that limits the number of snapshot shards requested.

Abstract: Disclosed are a channel device for surgery and a trigger structure. It aims at improving the problem that the operational efficiency of existing channel devices for surgery is not high. The channel device for surgery includes: a binding cord configured to be wound around a metal net; and a binding wire configured to pass through the binding cord and tighten up the binding cord, so as to compress the metal net, or configured to be pulled away from the binding cord, so as to loosen the binding cord and the metal net. In the trigger structure, different first locking portions are configured to cooperate with a first engaging portion, so as to drive the trolley to slide intermittently relative to the handle, such that a second engaging portion cooperates with different second locking portions, hereby locking the sliding trolley in different positions on the handle.

Abstract: An in-place data recovery method and system include receiving a user request to restore a virtual machine to a version corresponding to a first point in time, identifying a first snapshot of the virtual machine based on the user request, generating a second snapshot of the virtual machine, identifying a second data block in the second snapshot that includes modified data derived from data content of a first data block in the first snapshot, generating reverse incremental backup data including the first data block, and restoring the virtual machine in-place based on the reverse incremental backup data.

Abstract: A data management system having a storage appliance configured to store a snapshot of a virtual machine; and one or more processors in communication with the storage appliance. The one or more processors are configured to perform operations including: identifying a plurality of shards of the virtual machine; requesting a shard snapshot of each of the plurality of shards; receiving the shard snapshots asynchronously; ordering the received shard snapshots sequentially into a results queue; and storing a single snapshot of the virtual machine based on the ordered shard snapshots. The operations may further include maintaining a flow control queue that limits a number of the requested shard snapshots.

Abstract: A data management system comprises: a storage appliance configured to store a snapshot of a virtual machine; and one or more processors in communication with the storage appliance. The one or more processors are configured to perform operations including: identifying a plurality of shards of the virtual machine; requesting a snapshot of each of the plurality of shards; receiving the shards asynchronously; ordering the received snapshot shards sequentially into a results queue; and storing a single snapshot of the virtual machine based on the ordered snapshot shards. Operations may further include maintaining a flow control queue that limits the number of snapshot shards requested.

Abstract: Embodiments of the present disclosure provide a memory test method and a device thereof, an electronic device, and a computer-readable storage medium, which relate to the field of semiconductor device testing technologies. The method is executed by a built-in self-test circuit and includes: acquiring defect information of a first memory by testing the first memory; acquiring repair information of the first memory based on the defect information of the first memory; and storing the repair information of the first memory in a second memory.

Abstract: Apparatus and method for processing an image-charge/current signal for an ion(s) undergoing oscillatory motion within an ion analyser apparatus. The method comprises: obtaining a recording of the image-charge/current signal (20a-20e) in the time domain. Then, by a signal processing unit, a value for the period (T) of a periodic signal component is determined within the recorded signal. Subsequently, the recorded signal is segmented into a number of successive time segments [0;T] of duration corresponding to the period (T). These lime segments are then co-registered in a first time dimension (t1) defining the period (T). The co-registered time segments are then separated along a second time dimension (t2) transverse to the first time dimension (t1). This generates a stack of time segments collectively defining a 2-dimensional (2D) function. The 2D function varies both across the stack in the first time dimension and along the stack in the second time dimension.

Abstract: A memory test method and apparatus, an electronic device, and a computer-readable storage medium are provided. The method includes: obtaining a test instruction; generating, in response to the test instruction, a test clock signal, a to-be-tested address and to-be-tested data; determining a to-be-tested memory from memories of a storage device, the storage device including a self-test circuit; writing the to-be-tested data into a storage unit corresponding to the to-be-tested address of the to-be-tested memory; reading output data from the storage unit corresponding to the to-be-tested address of the to-be-tested memory; and comparing the to-be-tested data and the output data to obtain a test result of the to-be-tested memory. The self-test circuit disposed in the storage device is used to implement a memory test process. Thus, the dependency on automatic test equipment is reduced, thereby improving test speed and reducing test cost.

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, an electronic device, relating to the field of semiconductor device test technology. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, a memory chip can be used for storing test vectors for a control chip, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, and an electronic device, which relate to the field of semiconductor device test technologies. The control chip includes a built-in self-test BIST circuit. The method is performed by the BIST circuit. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

Abstract: Example embodiments relate generally to data resynchronization methods and systems in continuous data protection (CDP) and more specifically to an input and output (I/O) filtering framework and log management system to seek a near-zero recovery point objective (RPO).

Abstract: A method for modelling timing behavior using augmented sensitivity data for physical parameters is disclosed. The method includes acquiring timing library data and sensitivity data for a physical parameter associated with a circuit design, generating a timing behavior model for the circuit design based on the timing library data and sensitivity data for the physical parameter, and storing the timing behavior model. The timing behavior model reduces a difference between a current known best measurement associated with the circuit design and a static timing analysis timing for the circuit design.

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Abstract: Various embodiments of a method and apparatus for determining parametric timing yield and bottlenecks are disclosed which take into account correlation between electrical circuit paths through common timing arcs of an integrated circuit chip under design. Monte Carlo samples of timing arc delays are generated and used in computing timing yield and identify yield bottlenecks.

Abstract: A method for fabricating memory device includes: providing a substrate having a bottom electrode layer therein, forming a buffer layer and a mask layer on the buffer layer over the substrate, in contact with the bottom electrode layer, performing an advanced oxidation process on a sidewall of the buffer layer to form a resistive layer, which surrounds the whole sidewall of the buffer layer and extends upward vertically from the substrate, and forming, over the substrate, a noble metal layer and a top electrode layer on the noble metal layer, fully covering the resistive layer and the mask layer.

Abstract: A method includes: sending, by a first device, a first bit stream to a second device, where the first bit stream is sent over N logical lanes of a physical layer of the first device; sending, by the first device, a first trigger marker group to the second device, where the first trigger marker group is used to indicate that the sending of the first bit stream ends; and sending, by the first device, a second bit stream to the second device in response to the sending of the first trigger marker group, where the second bit stream is sent over P logical lanes of the physical layer of the first device, and both N and P are positive integers.

Abstract: Method and an apparatus are provided for indicating a fault status. The method includes: a first device determines N alignment marker AM groups, where the N AM groups include first indication information, the first indication information is used to indicate a fault status of R receiving logical lanes of the first device, and each of the N AM groups includes M pieces of alignment marker group lane AMGL information; and in an ith period of N periods, the first device respectively sends M pieces of AMGL information constituting an ith AM group to a second device over M transmitting logical lanes.