Abstract: A memory test method and apparatus, an electronic device, and a computer-readable storage medium are provided. The method includes: obtaining a test instruction; generating, in response to the test instruction, a test clock signal, a to-be-tested address and to-be-tested data; determining a to-be-tested memory from memories of a storage device, the storage device including a self-test circuit; writing the to-be-tested data into a storage unit corresponding to the to-be-tested address of the to-be-tested memory; reading output data from the storage unit corresponding to the to-be-tested address of the to-be-tested memory; and comparing the to-be-tested data and the output data to obtain a test result of the to-be-tested memory. The self-test circuit disposed in the storage device is used to implement a memory test process. Thus, the dependency on automatic test equipment is reduced, thereby improving test speed and reducing test cost.

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, an electronic device, relating to the field of semiconductor device test technology. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, a memory chip can be used for storing test vectors for a control chip, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, and an electronic device, which relate to the field of semiconductor device test technologies. The control chip includes a built-in self-test BIST circuit. The method is performed by the BIST circuit. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

Abstract: Example embodiments relate generally to data resynchronization methods and systems in continuous data protection (CDP) and more specifically to an input and output (I/O) filtering framework and log management system to seek a near-zero recovery point objective (RPO).

Abstract: A method for modelling timing behavior using augmented sensitivity data for physical parameters is disclosed. The method includes acquiring timing library data and sensitivity data for a physical parameter associated with a circuit design, generating a timing behavior model for the circuit design based on the timing library data and sensitivity data for the physical parameter, and storing the timing behavior model. The timing behavior model reduces a difference between a current known best measurement associated with the circuit design and a static timing analysis timing for the circuit design.

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Abstract: Various embodiments of a method and apparatus for determining parametric timing yield and bottlenecks are disclosed which take into account correlation between electrical circuit paths through common timing arcs of an integrated circuit chip under design. Monte Carlo samples of timing arc delays are generated and used in computing timing yield and identify yield bottlenecks.

Abstract: A method for fabricating memory device includes: providing a substrate having a bottom electrode layer therein, forming a buffer layer and a mask layer on the buffer layer over the substrate, in contact with the bottom electrode layer, performing an advanced oxidation process on a sidewall of the buffer layer to form a resistive layer, which surrounds the whole sidewall of the buffer layer and extends upward vertically from the substrate, and forming, over the substrate, a noble metal layer and a top electrode layer on the noble metal layer, fully covering the resistive layer and the mask layer.

Abstract: A method includes: sending, by a first device, a first bit stream to a second device, where the first bit stream is sent over N logical lanes of a physical layer of the first device; sending, by the first device, a first trigger marker group to the second device, where the first trigger marker group is used to indicate that the sending of the first bit stream ends; and sending, by the first device, a second bit stream to the second device in response to the sending of the first trigger marker group, where the second bit stream is sent over P logical lanes of the physical layer of the first device, and both N and P are positive integers.

Abstract: Method and an apparatus are provided for indicating a fault status. The method includes: a first device determines N alignment marker AM groups, where the N AM groups include first indication information, the first indication information is used to indicate a fault status of R receiving logical lanes of the first device, and each of the N AM groups includes M pieces of alignment marker group lane AMGL information; and in an ith period of N periods, the first device respectively sends M pieces of AMGL information constituting an ith AM group to a second device over M transmitting logical lanes.

Abstract: For each circuit element in a pair of launch and capture paths, a parameter value of the circuit element may be modified by a variation amount that is assigned to a class of circuit elements to which the circuit element belongs. Next, a timing slack may be computed for the pair of launch and capture paths.

Abstract: Example embodiments relate generally to data resynchronization methods and systems in continuous data protection (CDP) and more specifically to an input and output (I/O) filtering framework and log management system to seek a near-zero recovery point objective (RPO).

Abstract: The present invention relates to a structure of a memory device. The structure of a memory device includes a substrate, including a bottom electrode layer formed therein. A buffer layer is disposed on the substrate, in contact with the bottom electrode layer. A resistive layer surrounds a whole sidewall of the buffer layer, and extends upward vertically from the substrate. A mask layer is disposed on the buffer layer and the resistive layer. A noble metal layer is over the substrate, and fully covers the resistive layer and the mask layer. A top electrode layer is disposed on the noble metal layer.

Abstract: Disclosed is a control method for an audio device, the audio device includes a playing component and a display screen rotatably connected to the playing component, and the control method for the audio device includes the following steps: in response to detecting rotation of the display screen, acquiring a first rotation direction and a first rotation angle of the display screen in a preset three-dimensional coordinate system; determining a second rotation direction and a second rotation angle of display content on the display screen according to the first rotation direction and the first rotation angle, where the first rotation direction is opposite to the second rotation direction, and a difference between the second rotation angle and the first rotation angle is less than or equal to a preset value; and adjusting a display orientation of the display content according to the second rotation direction and the second rotation angle.

Abstract: Disclosed is a control method for an audio device, the audio device includes a playing component and a display screen rotatably connected to the playing component, and the control method for the audio device includes the following steps: detecting a position of a user; determining a rotation mode of the display screen according to the position; acquiring a display expression corresponding to the rotation mode; and displaying the display expression on the display screen, and controlling the display screen to operate according to the rotation mode. This disclosure further provides an audio device and a computer-readable storage medium. This application improves the user's interaction experience with the audio device.

Abstract: This application provides a biphenyl diaryl pyrimidine derivative with an aromatic heterocyclic structure, a pharmaceutically-acceptable salt, a stereoisomer, a hydrate and a solvate thereof, where the biphenyl diaryl pyrimidine derivative is shown in formula (I). This application also provides a pharmaceutical composition containing the biphenyl diaryl pyrimidine derivative, or a pharmaceutically-acceptable salt, a stereoisomer, a hydrate and a solvate thereof, and a pharmaceutically-acceptable carrier. This application further provides a method of treating AIDS by administering a therapeutically effective amount of the pharmaceutical composition to a patient in need.

Abstract: Embodiments provide for mitigating parametric yield loss of an integrated circuit (IC) design. In certain embodiments, a delay distribution associated with at least one cell disposed in the design is determined. A pin slack distribution associated with paths in which the at least one cell is disposed is determined. A residual distribution is determined based at least in part on the delay distribution and the pin slack distribution. Yield loss associated with the at least one cell is determined based at least in part on the delay distribution and the residual distribution. When it is determined that that the yield loss associated with the at least one cell exceeds a yield loss threshold, the at least one cell may be identified as a candidate for replacement with a replacement cell.

Abstract: Apparatus and method for processing an image-charge/current signal for an ion(s) undergoing oscillatory motion within an ion analyser apparatus. The method comprises: obtaining a recording of the image-charge/current signal (20a-20e) in the time domain. Then, by a signal processing unit, a value for the period (T) of a periodic signal component is determined within the recorded signal. Subsequently, the recorded signal is segmented into a number of successive time segments [0;T] of duration corresponding to the period (T). These lime segments are then co-registered in a first time dimension (t1) defining the period (T). The co-registered time segments are then separated along a second time dimension (t2) transverse to the first time dimension (t1). This generates a stack of time segments collectively defining a 2-dimensional (2D) function. The 2D function varies both across the stack in the first time dimension and along the stack in the second time dimension.

Abstract: Disclosed is a control method for an audio device, the audio device includes a wireless charging module and a display screen, and the control method for the audio device includes the following steps: in response to detecting a mobile device is placed on the audio device, acquiring a screen placement state of the mobile device, the screen placement state includes at least one of a screen flat state, a screen horizontal state and a screen vertical state; and displaying display content of the display screen on a screen of the mobile device according to the screen placement state. This disclosure further provides an audio device and a computer-readable storage medium. The problem that the display effect of the display screen of the audio device will be affected when the audio device performs wireless charging for the mobile device has been solved.