Patents by Inventor Li Feng

Li Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240042832
    Abstract: A modular air outlet assembly comprises at least two air outlet sub-modules and a housing connecting member, wherein each of the air outlet sub-modules have different functions and are matchingly engaged in a sealed manner, and the air outlet sub-modules comprise a front sub-module and a rear sub-module; the front sub-module comprises a front housing and a front functional component, and the front housing has a standard air inlet joint; the rear sub-module comprises a rear housing and a rear functional component, and the rear housing has a standard air outlet joint and a standard air duct opening joint. A modular approach is used to design the air outlet assembly, and the relative angle between the air outlet sub-modules can be adjusted by means of different housing connecting members to avoid installation limitations in vehicles, and the mold development cost and related costs are reduced.
    Type: Application
    Filed: March 21, 2022
    Publication date: February 8, 2024
    Inventors: Shi Qiang LIN, Li Feng HUANG, Lin LI, Hong Jun CHEN, Zhe XU, Zeng Feng HUANG
  • Publication number: 20240021614
    Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.
    Type: Application
    Filed: August 4, 2023
    Publication date: January 18, 2024
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Li-Feng Teng, Li-Jung Liu
  • Publication number: 20230402729
    Abstract: The present invention provides a retaining component, a battery assembly and an end structure. The retaining component of the present invention is configured to fix multiple cells at the top and/or bottom of the multiple cells, and a hole open to the outside is provided in the retaining component at a position corresponding to a fusible part, so that the fusible part is exposed. According to the present invention, the fusible part can be exposed to the outside at the opening; this provides space for melt-through of the fusible part. For example, when melt-through occurs due to current flow through the fusible part of a collector component, the structure of the opening allows the fusible part to melt through fully, thereby protecting the circuit.
    Type: Application
    Filed: May 18, 2023
    Publication date: December 14, 2023
    Inventors: Hei Man LEE, Nan Wang, Li Feng Wang
  • Patent number: 11830875
    Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Li-Feng Teng, Li-Jung Liu
  • Publication number: 20230378327
    Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 23, 2023
    Inventors: Chen-Wei PAN, Jen-Chih HSUEH, Li-Feng CHU, Chih-Teng LIAO
  • Publication number: 20230380155
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 23, 2023
    Inventors: Wei Cheng WU, Li-Feng TENG
  • Publication number: 20230378565
    Abstract: The present invention provides a battery support, and a battery assembly comprising the battery support. The battery support is used to retain a battery assembly having multiple cells; a heat dissipating means of the battery support comprises at least one spacer component, the spacer component has multiple accommodating recesses on at least one side, the accommodating recess is partially shape-fitted to a circumferential sidewall of the cell, and the spacer component is made of a material with a thermal conductivity greater than that of air. The heat dissipating means of the battery support of the present invention is fitted to outer walls of the cells over as large an area as possible, and the heat dissipating means is able to undergo heat exchange with the cells in the process of use of the battery assembly and thus promote heat dissipation from the cells, in order to maintain the efficiency of use and the service life of the battery assembly.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 23, 2023
    Inventors: Hei Man LEE, Nan Wang, Li Feng Wang
  • Publication number: 20230371427
    Abstract: A robotic garden tool including a deck, a blade motor configured to rotate a blade about a blade axis, and a mount axially movable with respect to the deck along the blade axis. The garden tool also includes a worm shaft mounted for rotation with respect to the deck about a worm axis, the work shaft forming a threaded interface with the mount such that rotation of the worm shaft about the worm axis causes the mount to move axially with respect to the deck. The garden tool also includes a manual actuator configured to move with respect to the deck in response to receiving a manual actuation force by an operator, where the manual actuator is in operable communication with the worm shaft such that movement of the manual actuator with respect to the deck causes the worm shaft to rotate about the worm axis.
    Type: Application
    Filed: September 1, 2022
    Publication date: November 23, 2023
    Inventors: Hok Sum Sam LAI, Ho Lam NG, Li Feng WANG, Yong HU
  • Patent number: 11824103
    Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: November 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Wei Pan, Jen-Chih Hsueh, Li-Feng Chu, Chih-Teng Liao
  • Patent number: 11825651
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Cheng Wu, Li-Feng Teng
  • Publication number: 20230352482
    Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure, a first gate spacer and a second gate spacer. The first gate spacer includes a first layer, a second layer over the first layer, a third layer over the second layer, a fourth layer over the third layer, and a fifth layer of the fourth layer, in which the first layer, the third layer, and the fifth layer of the first gate spacer are made of a same material. The second gate spacer includes a first layer, a second layer over the first layer, and a third layer over the second layer, in which the first layer and the third layer of the second gate spacer are made of a same material, and in which a lateral width of the first gate spacer is greater than a lateral width of the second gate spacer.
    Type: Application
    Filed: July 7, 2023
    Publication date: November 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Feng TENG, Wei-Cheng WU, Harry-Hak-Lay CHUANG, Li-Jung LIU
  • Publication number: 20230301075
    Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 21, 2023
    Inventors: Meng-Han Lin, Te-Hsin Chiu, Wei-Cheng Wu, Li-Feng Teng, Chien-Hung Chang
  • Patent number: 11754494
    Abstract: A device for simultaneously measuring mercury, cadmium, zinc, and lead is provided, including: a gas generating device; a quartz analysis tube connected to the gas generating device, and the quartz analysis tube includes a sample heating zone, a high-temperature packing zone and a quartz collimating tube; an atomic absorption detection device AA1 arranged behind the quartz analysis tube, where the atomic absorption detection device includes an atomic absorption detector, a flame, and a light source; a quartz catalytic tube arranged behind the atomic absorption detection device, where the quartz catalytic tube includes a flame buffer zone and an adsorption packing zone; and an atomic absorption mercury measuring device arranged behind the quartz catalytic tube, where the atomic absorption mercury measuring device includes a mercury enrichment tube, an atomic absorption detector AA2 and an air pump.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: September 12, 2023
    Assignee: CHANGSHA KAIYUAN HONGSHENG TECHNOLOGY CO., LTD
    Inventors: Li Feng, Guo Sun, Te Xiao
  • Patent number: 11758721
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate. A second dielectric layer is disposed between the floating gate and the control gate, having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof. A third dielectric layer is disposed between the second dielectric layer and the control gate, and includes a dielectric material having a dielectric constant higher than silicon nitride.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei Cheng Wu, Li-Feng Teng
  • Publication number: 20230279504
    Abstract: The invention discloses a fluorescent quantitative PCR technology-based method for distinguishing human DNA, and a fluorescent quantitative PCR technology-based composition or kit for distinguishing human DNA, comprising primers and/or probes of nucleotide sequences.
    Type: Application
    Filed: January 25, 2019
    Publication date: September 7, 2023
    Inventors: Li FENG, Xiaoyan LENG, Yunjuan WANG, Hui LIU
  • Patent number: 11742348
    Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure, a first gate spacer and a second gate spacer. The first gate spacer includes a first layer, a second layer over the first layer, a third layer over the second layer, a fourth layer over the third layer, and a fifth layer of the fourth layer, in which the first layer, the third layer, and the fifth layer of the first gate spacer are made of a same material. The second gate spacer includes a first layer, a second layer over the first layer, and a third layer over the second layer, in which the first layer and the third layer of the second gate spacer are made of a same material, and in which a lateral width of the first gate spacer is greater than a lateral width of the second gate spacer.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Feng Teng, Wei-Cheng Wu, Harry-Hak-Lay Chuang, Li-Jung Liu
  • Publication number: 20230260942
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) having a first IC structure that includes a first substrate, a first interconnect structure, and a first hybrid bond structure. The second IC structure includes a second substrate and a second hybrid bond structure abutting the first hybrid bond structure at a bond interface. The second substrate includes first and second device regions including first semiconductor devices and second semiconductor devices. The first semiconductor devices being of a first type of IC device and the second semiconductor devices being of a second type of IC device different than the first type of IC device. A bond routing structure couples the first interconnect structure to the first and second semiconductor devices. A lateral routing structure continuously laterally extends from under the first device region to under the second device region.
    Type: Application
    Filed: May 23, 2022
    Publication date: August 17, 2023
    Inventors: Harry-Hak-Lay Chuang, Li-Feng Teng, Wei Cheng Wu
  • Publication number: 20230245987
    Abstract: The present disclosure relates integrated chip structure. The integrated chip structure includes one or more interconnects disposed within a dielectric structure over a substrate. A bond pad having a top surface is arranged along a top surface of the dielectric structure. The top surface of the bond pad includes a plurality of discrete top surface segments that are laterally separated from one another by non-zero distances that extend between interior sidewalls of the bond pad, as viewed in a cross-sectional view. The dielectric structure is disposed directly between the interior sidewalls of the bond pad.
    Type: Application
    Filed: May 23, 2022
    Publication date: August 3, 2023
    Inventors: Harry-Hak-Lay Chuang, Li-Feng Teng, Wei Cheng Wu
  • Patent number: 11706914
    Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Lin, Te-Hsin Chiu, Wei-Cheng Wu, Li-Feng Teng, Chien-Hung Chang
  • Publication number: 20230160813
    Abstract: A device for simultaneously measuring mercury, cadmium, zinc, and lead is provided, including: a gas generating device; a quartz analysis tube connected to the gas generating device, and the quartz analysis tube includes a sample heating zone, a high-temperature packing zone and a quartz collimating tube; an atomic absorption detection device AA1 arranged behind the quartz analysis tube, where the atomic absorption detection device includes an atomic absorption detector, a flame, and a light source; a quartz catalytic tube arranged behind the atomic absorption detection device, where the quartz catalytic tube includes a flame buffer zone and an adsorption packing zone; and an atomic absorption mercury measuring device arranged behind the quartz catalytic tube, where the atomic absorption mercury measuring device includes a mercury enrichment tube, an atomic absorption detector AA2 and an air pump.
    Type: Application
    Filed: November 21, 2019
    Publication date: May 25, 2023
    Applicant: CHANGSHA KAIYUAN HONGSHENG TECHNOLOGY CO., LTD
    Inventors: Li FENG, Guo SUN, Te XIAO