Abstract: The instant disclosure provides a gate device and an umbrella sharing system which utilizes the gate device. The gate device includes a base, an actuator, a pair of gate plates, and an identification sensor. The actuator is disposed on a top surface of the base and includes a latch extending downward through the base. The pair of gate plates are disposed on a bottom surface of the base, and each of the gate plates includes a guiding structure and a locking structure. A waiting zone for receiving an umbrella is defined between the two guiding structures. The latch of the actuator is driven to engage with the locking structures to limit the movement of the gate plates. The identification sensor is above the waiting zone and disposed on the base and is configured to identify the identity of an umbrella which enters the waiting zone.

Abstract: Systems and techniques are provided for processing one or more images. For instance, aspects include a process that can include determining a first region of interest corresponding to a first object depicted in an image obtained using at least one camera. The first region of interest is associated with at least one element of a multi-point grid associated with a multi-point depth sensing system. The process can include determining a first extended region of interest for the first object. The first extended region of interest is associated with a plurality of elements including the at least one element and one or more additional elements of the multi-point grid. The process can further include, based on the plurality of elements associated with the first extended region of interest, determining representative depth information representing a first distance between the at least one camera and the first object depicted in the image.

Abstract: Techniques and systems are provided for improving one or more image capture operations. In some examples, a system determines, based on data from one or more sensors, a movement of an image capture device associated with a capture of a plurality of image frames. The systems adjust a position of at least one object in each of the plurality of image frames based on the movement of the image capture device. The system determines a motion of the at least one object based on a difference in the adjusted position among the plurality of image frames. The system selects a value for at least one image capture parameter associated with the plurality of image frames based on the motion of the at least one object.

Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

Abstract: A linear movement bistable electromagnetic switch, comprising a coil (1), a magnetic rotor (2) movably disposed in an inner hole of the coil (1), a shell (3) which wraps an outer side surface of the coil (1), and an insulating layer (4) disposed between the coil (1) and the shell (3). The magnetic rotor (2) is able to move under the effect of a magnetic field generated after the coil is energized; one end of the magnetic rotor (2) extends out of the coil (1) and is connected to a blocking piece (211) for opening/closing a loudspeaker leakage hole. The magnetic rotor is able to be extended or retracted by changing the direction of current in the coil so as to drive the blocking piece to block or open the leakage hole, such that the call distortion condition can be improved and the high-frequency sound effect will not be reduced.

Abstract: A method of operating a cleaning system is provided herein. The method includes receiving a first battery pack including a first battery controller, receiving a first signal from the first battery controller, outputting, in response to receiving the first signal, a first control signal, operating a motor at a first predetermined constant power based on the first control signal, receiving a second battery pack including a second battery controller, receiving a second signal from the second battery controller, outputting, in response to receiving the second signal, a second control signal, and operating the motor at a second predetermined constant power based on the second control signal.

Abstract: Described is an approach for tracking 3D organ motion in real-time using magnetic resonance imaging (MRI). The approach may include offline learning, which may acquire signature and 3D imaging data over multiple respiratory cycles to create a database of high-resolution 3D motion states. The approach may further include online matching, which may acquire signature data only in real-time (latency less than 0.2 seconds). From a motion state and motion signature database, the 3D motion state whose signature best (or sufficiently) matches the newly-acquired signature data may be selected. Real-time 3D motion tracking may be accomplished by performing time-consuming acquisition and reconstruction work in an offline learning phase, leaving just signature acquisition and correlation analysis in an online matching step, minimizing or otherwise reducing latency. The approach may be used to adapt radiotherapy procedures based on tumor motion using a magnetic resonance linear accelerator (MR-Linac) system.

Abstract: A semiconductor device includes a first die having a first bonding layer; a second die having a second bonding layer disposed over and bonded to the first bonding layer; a plurality of bonding members, wherein each of the plurality of bonding members extends within the first bonding layer and the second bonding layer, wherein the plurality of bonding members includes a connecting member electrically connected to a first conductive pattern in the first die and a second conductive pattern in the second die, and a dummy member electrically isolated from the first conductive pattern and the second conductive pattern; and an inductor disposed within the first bonding layer and the second bonding layer. A method of manufacturing a semiconductor device includes bonding a first inductive coil of a first die to a second inductive coil of a second die to form an inductor.

Abstract: A modular air outlet assembly comprises at least two air outlet sub-modules and a housing connecting member, wherein each of the air outlet sub-modules have different functions and are matchingly engaged in a sealed manner, and the air outlet sub-modules comprise a front sub-module and a rear sub-module; the front sub-module comprises a front housing and a front functional component, and the front housing has a standard air inlet joint; the rear sub-module comprises a rear housing and a rear functional component, and the rear housing has a standard air outlet joint and a standard air duct opening joint. A modular approach is used to design the air outlet assembly, and the relative angle between the air outlet sub-modules can be adjusted by means of different housing connecting members to avoid installation limitations in vehicles, and the mold development cost and related costs are reduced.

Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

Abstract: The present invention provides a retaining component, a battery assembly and an end structure. The retaining component of the present invention is configured to fix multiple cells at the top and/or bottom of the multiple cells, and a hole open to the outside is provided in the retaining component at a position corresponding to a fusible part, so that the fusible part is exposed. According to the present invention, the fusible part can be exposed to the outside at the opening; this provides space for melt-through of the fusible part. For example, when melt-through occurs due to current flow through the fusible part of a collector component, the structure of the opening allows the fusible part to melt through fully, thereby protecting the circuit.

Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.

Abstract: The present invention provides a battery support, and a battery assembly comprising the battery support. The battery support is used to retain a battery assembly having multiple cells; a heat dissipating means of the battery support comprises at least one spacer component, the spacer component has multiple accommodating recesses on at least one side, the accommodating recess is partially shape-fitted to a circumferential sidewall of the cell, and the spacer component is made of a material with a thermal conductivity greater than that of air. The heat dissipating means of the battery support of the present invention is fitted to outer walls of the cells over as large an area as possible, and the heat dissipating means is able to undergo heat exchange with the cells in the process of use of the battery assembly and thus promote heat dissipation from the cells, in order to maintain the efficiency of use and the service life of the battery assembly.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

Abstract: A robotic garden tool including a deck, a blade motor configured to rotate a blade about a blade axis, and a mount axially movable with respect to the deck along the blade axis. The garden tool also includes a worm shaft mounted for rotation with respect to the deck about a worm axis, the work shaft forming a threaded interface with the mount such that rotation of the worm shaft about the worm axis causes the mount to move axially with respect to the deck. The garden tool also includes a manual actuator configured to move with respect to the deck in response to receiving a manual actuation force by an operator, where the manual actuator is in operable communication with the worm shaft such that movement of the manual actuator with respect to the deck causes the worm shaft to rotate about the worm axis.

Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure, a first gate spacer and a second gate spacer. The first gate spacer includes a first layer, a second layer over the first layer, a third layer over the second layer, a fourth layer over the third layer, and a fifth layer of the fourth layer, in which the first layer, the third layer, and the fifth layer of the first gate spacer are made of a same material. The second gate spacer includes a first layer, a second layer over the first layer, and a third layer over the second layer, in which the first layer and the third layer of the second gate spacer are made of a same material, and in which a lateral width of the first gate spacer is greater than a lateral width of the second gate spacer.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.