Abstract: The provided is a remote sensing observation equipment, including a base and a remote sensing observation instrument, the remote sensing observation instrument is located above the base, a lifting mechanism is arranged between the remote sensing observation instrument and the base, a sliding groove is arranged on both sides of the middle part of the base, both of the sliding grooves are slidingly assembled with sliding seats, both of the sliding seats are fixed with a first protective shell, the ends of the two first protective shells are abut against each other and located outside the remote sensing observation instrument, a fixed mechanism is arranged between the sliding seat and the sliding groove; protecting the remote sensing observation instrument through the first protective shell and the second protective shell being closed to each other, avoids the instrument being damaged by collision, and prolongs the service life of the instrument.

Abstract: A semiconductor device includes a substrate, an isolation structure, a conductive structure, and a first contact structure. The isolation structure is disposed in the substrate. The conductive structure is disposed on the isolation structure. The conductive structure extends upwards from the isolation structure, in which the first contact structure has a top portion on the conductive structure and a bottom portion in contact with the isolation structure.

Abstract: Provided is a three-phase system V2O3/VN/Mo2C nanoelectrode material, and a preparation method and application thereof. The nanoelectrode material comprises V2O3 particles, VN particles, and Mo2C particles. The V2O3 particles, VN particles, and Mo2C particles are interlaced in lattice stripes and are uniformly distributed. The mass ratio of the V2O3, VN and Mo2C is (1 to 4):(10 to 40):(4 to 16). The above-mentioned three kinds of nanoparticles are intertwined to form more incoherent interface area. The increase in the area of the incoherent interface area will cause more defects, so that more active sites are provided, and the hydrogen production performance is improved.

Abstract: Described is an approach for tracking 3D organ motion in real-time using magnetic resonance imaging (MRI). The approach may include offline learning, which may acquire signature and 3D imaging data over multiple respiratory cycles to create a database of high-resolution 3D motion states. The approach may further include online matching, which may acquire signature data only in real-time (latency less than 0.2 seconds). From a motion state and motion signature database, the 3D motion state whose signature best (or sufficiently) matches the newly-acquired signature data may be selected. Real-time 3D motion tracking may be accomplished by performing time-consuming acquisition and reconstruction work in an offline learning phase, leaving just signature acquisition and correlation analysis in an online matching step, minimizing or otherwise reducing latency. The approach may be used to adapt radiotherapy procedures based on tumor motion using a magnetic resonance linear accelerator (MR-Linac) system.

Abstract: A semiconductor packaging assembly includes a circuit board, at least one chip, a packaging body, and wires. The circuit board includes a first surface, a second surface opposite to the first surface, at least one receiving hole recessed from the first surface, and first welding pads on the first surface. The chip is received in the receiving hole and spaced apart from the circuit board by a gap. Each chip includes an active surface opposite to the second surface, a passive surface opposite to the active surface, and pins on the active surface. The packaging body is received in the gap and bonded to the chip and the circuit board. The wires are attached to a third surface of the packaging body opposite to the second surface and each wire is electrically connected to at least one of the pins and at least one of the first welding pads.

Abstract: A water treatment device based on micro-nano bubble technology includes the micro-nano bubble generation device and the sewage tank, the sewage tank is also installed with water surface sewage collection mechanism and water surface sewage cleaning mechanism, the water surface sewage collection mechanism includes the pushing plate and the first transmission component, the pushing plate and the sewage tank are slidingly connected, and the pushing plate is also fixedly connected to the limit connecting rod, the water surface sewage cleaning mechanism includes the cleaning sieve plate and the sewage collecting box, and the cleaning sieve plate is vertically arranged inside the sewage tank, and the sewage tank is fixedly connected with the hinged table, the hinged table is connected with the first rotating shaft and the rear wall of the sewage tank is also equipped with the second transmission component.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Abstract: Various embodiments of the present application are directed to an IC device and associated forming methods. In some embodiments, a memory region and a logic region are integrated in a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices disposed on a plurality of logic sub-regions of the logic region. A first logic device is disposed on a first upper surface of a first logic sub-region. A second logic device is disposed on a second upper surface of a second logic sub-region. A third logic device is disposed on a third upper surface of a third logic sub-region. Heights of the first, second, and third upper surfaces of the logic sub-regions monotonically decrease. By arranging logic devices on multiple recessed positions of the substrate, design flexibility is improved and devices with multiple operation voltages are better suited.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer, and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Abstract: An autofocus camera module includes a circuit board with a plurality of driving elements, and a lens mechanism disposed on the circuit board assembly. The lens mechanism includes a first lens assembly, a second lens assembly, and a liquid lens disposed between the first lens assembly and the second lens assembly. The first lens assembly includes a first lens holder, a first lens group housed inside the first lens holder, and a first conductive line disposed on a surface of the lens hold, the first lens holder is connected to one side of the circuit board assembly. The liquid lens includes connecting pads, and each connecting pad is disposed with a solder material, the connecting pads are soldered to the first lens holder through the solder material, the conductive line electrically connects the connecting pads and the plurality of driving elements.

Abstract: Various embodiments of the present application are directed to an IC device and associated forming methods. In some embodiments, a memory region and a logic region are integrated in a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices disposed on a plurality of logic sub-regions of the logic region. A first logic device is disposed on a first upper surface of a first logic sub-region. A second logic device is disposed on a second upper surface of a second logic sub-region. A third logic device is disposed on a third upper surface of a third logic sub-region. Heights of the first, second, and third upper surfaces of the logic sub-regions monotonically decrease. By arranging logic devices on multiple recessed positions of the substrate, design flexibility is improved and devices with multiple operation voltages are better suited.

Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

Abstract: The present application relates to the technical field of electromagnetic-isolation shielding materials, and in particular to a heat-resistant nanocrystalline magnetic-isolation shielding material and a preparation method and application thereof. The preparation method includes the following steps: S1, applying a double-sided adhesive tape onto a nanocrystalline soft-magnetic alloy ribbon to prepare a adhesive-coated nanocrystalline ribbon; S2, performing primary magnet cracking treatment on the adhesive-coated nanocrystalline ribbon to obtain a single-layered nanocrystalline magnetic layer; S3, performing multi-layer combination on the single-layered nanocrystalline magnetic layer to obtain a composite, and performing stress relief treatment on the composite to obtain a multi-layered nanocrystalline magnetic layer; and S4: performing secondary magnet cracking treatment on the multi-layered nanocrystalline magnetic layer to obtain a heat-resistant nanocrystalline magnetic-isolation shielding material.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

Abstract: A linear movement bistable electromagnetic switch, comprising a coil (1), a magnetic rotor (2) movably disposed in an inner hole of the coil (1), a shell (3) which wraps an outer side surface of the coil (1), and an insulating layer (4) disposed between the coil (1) and the shell (3). The magnetic rotor (2) is able to move under the effect of a magnetic field generated after the coil is energized; one end of the magnetic rotor (2) extends out of the coil (1) and is connected to a blocking piece (211) for opening/closing a loudspeaker leakage hole. The magnetic rotor is able to be extended or retracted by changing the direction of current in the coil so as to drive the blocking piece to block or open the leakage hole, such that the call distortion condition can be improved and the high-frequency sound effect will not be reduced.

Abstract: A method of operating a cleaning system is provided herein. The method includes receiving a first battery pack including a first battery controller, receiving a first signal from the first battery controller, outputting, in response to receiving the first signal, a first control signal, operating a motor at a first predetermined constant power based on the first control signal, receiving a second battery pack including a second battery controller, receiving a second signal from the second battery controller, outputting, in response to receiving the second signal, a second control signal, and operating the motor at a second predetermined constant power based on the second control signal.

Abstract: Described is an approach for tracking 3D organ motion in real-time using magnetic resonance imaging (MRI). The approach may include offline learning, which may acquire signature and 3D imaging data over multiple respiratory cycles to create a database of high-resolution 3D motion states. The approach may further include online matching, which may acquire signature data only in real-time (latency less than 0.2 seconds). From a motion state and motion signature database, the 3D motion state whose signature best (or sufficiently) matches the newly-acquired signature data may be selected. Real-time 3D motion tracking may be accomplished by performing time-consuming acquisition and reconstruction work in an offline learning phase, leaving just signature acquisition and correlation analysis in an online matching step, minimizing or otherwise reducing latency. The approach may be used to adapt radiotherapy procedures based on tumor motion using a magnetic resonance linear accelerator (MR-Linac) system.

Abstract: A semiconductor device includes a first die having a first bonding layer; a second die having a second bonding layer disposed over and bonded to the first bonding layer; a plurality of bonding members, wherein each of the plurality of bonding members extends within the first bonding layer and the second bonding layer, wherein the plurality of bonding members includes a connecting member electrically connected to a first conductive pattern in the first die and a second conductive pattern in the second die, and a dummy member electrically isolated from the first conductive pattern and the second conductive pattern; and an inductor disposed within the first bonding layer and the second bonding layer. A method of manufacturing a semiconductor device includes bonding a first inductive coil of a first die to a second inductive coil of a second die to form an inductor.