Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

Abstract: A cell culture platform includes a base plate, multiple through holes formed in the base plate, and a support wall extending downward from the periphery of the base plate. The base plate has a top surface and a bottom surface opposite to the top surface. The through holes traverse the top surface and bottom surface of the base plate. Each of the through holes has an upper opening and a lower opening, and the aperture gradually tapers from the upper opening to the lower opening. The support wall defines an accommodating space beneath the base plate. The structural design of the cell culture platform allows for the formation of larger hanging drop during cell suspension culture. Additionally, the cell culture platform can be used as an adapter, which is compatible with covers and 96-well plates of any brand.

Abstract: A stenosis assessment method and device based on the intracranial digital subtraction angiographic (DSA) imaging, including acquiring the intracranial DSA imaging and extracting two planar images containing the target blood vessel from the DSA imaging, wherein the two planar images have different shooting angles. According to the two planar images, a 3D model of the target vessel is established. Based on the established 3D model of the target vessel and the DSA imaging, the hemodynamic simulation of the target vessel is performed. The disclosure realizes the functional assessment of intracranial vascular stenosis, improves the diagnostic accuracy, and provides certain assistance for neurologists to determine intervention means. The disclosure of noninvasive FFR technology in the assessment of intracranial vascular stenosis can only rely on angiography for functional assessment, saving the medical examination cost of patients. It has more convenient operation and higher repeatability.

Abstract: A package structure of an optical emission module and a preparation method thereof are provided. The package structure includes a substrate module and an optical emission module. The substrate module includes a substrate, and multiple channels are defined in the substrate module. The optical emission module is located on the substrate. Two ends of each channel extend to the substrate and the optical emission module, respectively. An inner wall of each channel is provided with a conductive layer to form a hollow conductive channel. The hollow conductive channel is electrically connected to the substrate and the optical emission module.

Abstract: A packaging structure, a preparation method, and a camera module are provided. The packaging structure includes a substrate module, and a light emitting unit and a light receiving unit located on the substrate of the substrate module. The substrate module defines first channels and second channels. Two ends of each first channel extend to the substrate and the non-photosensitive area of the light receiving unit, respectively. A first conductive layer is formed on an inner wall of each first channel to form a first hollow conductive channel, which is electrically connected to the substrate and the non-photosensitive area. Two ends of each second channel extend to the substrate and the light emitting unit, respectively. A second conductive layer is formed on an inner wall of each second channel to form a second hollow conductive channel, which is electrically connected to the substrate and the light emitting unit.

Abstract: A semiconductor device includes a substrate, an isolation structure, a conductive structure, and a first contact structure. The isolation structure is disposed in the substrate. The conductive structure is disposed on the isolation structure. The conductive structure extends upwards from the isolation structure, in which the first contact structure has a top portion on the conductive structure and a bottom portion in contact with the isolation structure.

Abstract: The present disclosure relates integrated chip structure. The integrated chip structure includes one or more interconnects disposed within a dielectric structure over a substrate. A bond pad having a top surface is arranged along a top surface of the dielectric structure. The top surface of the bond pad includes a plurality of discrete top surface segments that are laterally separated from one another by non-zero distances that extend between interior sidewalls of the bond pad, as viewed in a cross-sectional view. The dielectric structure is disposed directly between the interior sidewalls of the bond pad.

Abstract: A method of producing a photonic package is provided. A first wafer comprising a plurality of optical dies is disposed over a carrier, wherein each of the optical dies include a front side and a back side opposite to the front side, and wherein the front side of each of the optical dies face the carrier. The first wafer is bonded to a second wafer including a plurality of electronic dies, wherein each of the electronic dies include a front side and a back side opposite to the front side, and wherein the front side of each of the optical dies face the back side of each of the electronic dies, respectively. The carrier is removed from the first wafer. The bonded first wafer and second wafer is divided into a plurality of photonic package.

Abstract: The provided is a remote sensing observation equipment, including a base and a remote sensing observation instrument, the remote sensing observation instrument is located above the base, a lifting mechanism is arranged between the remote sensing observation instrument and the base, a sliding groove is arranged on both sides of the middle part of the base, both of the sliding grooves are slidingly assembled with sliding seats, both of the sliding seats are fixed with a first protective shell, the ends of the two first protective shells are abut against each other and located outside the remote sensing observation instrument, a fixed mechanism is arranged between the sliding seat and the sliding groove; protecting the remote sensing observation instrument through the first protective shell and the second protective shell being closed to each other, avoids the instrument being damaged by collision, and prolongs the service life of the instrument.

Abstract: A semiconductor device includes a substrate, an isolation structure, a conductive structure, and a first contact structure. The isolation structure is disposed in the substrate. The conductive structure is disposed on the isolation structure. The conductive structure extends upwards from the isolation structure, in which the first contact structure has a top portion on the conductive structure and a bottom portion in contact with the isolation structure.

Abstract: Provided is a three-phase system V2O3/VN/Mo2C nanoelectrode material, and a preparation method and application thereof. The nanoelectrode material comprises V2O3 particles, VN particles, and Mo2C particles. The V2O3 particles, VN particles, and Mo2C particles are interlaced in lattice stripes and are uniformly distributed. The mass ratio of the V2O3, VN and Mo2C is (1 to 4):(10 to 40):(4 to 16). The above-mentioned three kinds of nanoparticles are intertwined to form more incoherent interface area. The increase in the area of the incoherent interface area will cause more defects, so that more active sites are provided, and the hydrogen production performance is improved.

Abstract: Described is an approach for tracking 3D organ motion in real-time using magnetic resonance imaging (MRI). The approach may include offline learning, which may acquire signature and 3D imaging data over multiple respiratory cycles to create a database of high-resolution 3D motion states. The approach may further include online matching, which may acquire signature data only in real-time (latency less than 0.2 seconds). From a motion state and motion signature database, the 3D motion state whose signature best (or sufficiently) matches the newly-acquired signature data may be selected. Real-time 3D motion tracking may be accomplished by performing time-consuming acquisition and reconstruction work in an offline learning phase, leaving just signature acquisition and correlation analysis in an online matching step, minimizing or otherwise reducing latency. The approach may be used to adapt radiotherapy procedures based on tumor motion using a magnetic resonance linear accelerator (MR-Linac) system.

Abstract: A semiconductor packaging assembly includes a circuit board, at least one chip, a packaging body, and wires. The circuit board includes a first surface, a second surface opposite to the first surface, at least one receiving hole recessed from the first surface, and first welding pads on the first surface. The chip is received in the receiving hole and spaced apart from the circuit board by a gap. Each chip includes an active surface opposite to the second surface, a passive surface opposite to the active surface, and pins on the active surface. The packaging body is received in the gap and bonded to the chip and the circuit board. The wires are attached to a third surface of the packaging body opposite to the second surface and each wire is electrically connected to at least one of the pins and at least one of the first welding pads.

Abstract: A water treatment device based on micro-nano bubble technology includes the micro-nano bubble generation device and the sewage tank, the sewage tank is also installed with water surface sewage collection mechanism and water surface sewage cleaning mechanism, the water surface sewage collection mechanism includes the pushing plate and the first transmission component, the pushing plate and the sewage tank are slidingly connected, and the pushing plate is also fixedly connected to the limit connecting rod, the water surface sewage cleaning mechanism includes the cleaning sieve plate and the sewage collecting box, and the cleaning sieve plate is vertically arranged inside the sewage tank, and the sewage tank is fixedly connected with the hinged table, the hinged table is connected with the first rotating shaft and the rear wall of the sewage tank is also equipped with the second transmission component.

Abstract: Various embodiments of the present application are directed to an IC device and associated forming methods. In some embodiments, a memory region and a logic region are integrated in a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices disposed on a plurality of logic sub-regions of the logic region. A first logic device is disposed on a first upper surface of a first logic sub-region. A second logic device is disposed on a second upper surface of a second logic sub-region. A third logic device is disposed on a third upper surface of a third logic sub-region. Heights of the first, second, and third upper surfaces of the logic sub-regions monotonically decrease. By arranging logic devices on multiple recessed positions of the substrate, design flexibility is improved and devices with multiple operation voltages are better suited.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer, and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Abstract: An autofocus camera module includes a circuit board with a plurality of driving elements, and a lens mechanism disposed on the circuit board assembly. The lens mechanism includes a first lens assembly, a second lens assembly, and a liquid lens disposed between the first lens assembly and the second lens assembly. The first lens assembly includes a first lens holder, a first lens group housed inside the first lens holder, and a first conductive line disposed on a surface of the lens hold, the first lens holder is connected to one side of the circuit board assembly. The liquid lens includes connecting pads, and each connecting pad is disposed with a solder material, the connecting pads are soldered to the first lens holder through the solder material, the conductive line electrically connects the connecting pads and the plurality of driving elements.