Abstract: A radio frequency (RF) receiver has an antenna, a low-noise amplifier, a sigma-delta frequency synthesizer/voltage-controlled oscillator (VCO), an in-phase and quadrature (I/Q) mixer, a channel filter, and a digital baseband circuit. The digital baseband circuit has a demodulator, a preamble detection and carrier frequency offset (CFO) estimation circuit, and a CFO to sigma-delta modulation (SDM) input mapper. A preamble field of a digital demodulated signal generated by the demodulator is detected by the preamble detection and CFO estimation circuit. The RF receiver simultaneously compensates its CFO and optimizes a bandwidth of the channel filter based on the detection of the preamble field of the digital demodulated signal by the preamble detection and CFO estimation circuit.

Abstract: A motor module (100) for an electrically driven garden tool comprises: a brushless DC motor (102) having a motor drive shaft (104); and a gearbox having an output shaft (108), the gearbox configured to receive the motor drive shaft (104) from the brushless DC motor (102) and drive a rotary element of the electrically driven garden tool with the output shaft (108), wherein the gearbox having a gear reduction ratio of at least 2:1. An electrically driven garden tool comprises: a housing (602) comprising a receptacle for receiving a motor module (100); and a rotary element drivable with an electric motor, the rotary element comprises a receiving element having a keyed interface corresponding to the keyed surface (122) or structure on the output shaft (108) of the motor module (100).

Abstract: An interface (30) between a battery and an electrical device, the interface (30) comprising: a male terminal (24) and a female terminal (26) configured to receive the male terminal (24); the female terminal (26) having a female contact (36) of conductive material and the male terminal (24) having a male contact (32) of conductive material; wherein, at least one of the female contact (36) and the male contact (32) are resiliently deformable such that insertion of the male terminal (24) in the female terminal (26) provides an area (40) of face to face contact in which the male contact (32) and the female contact (36) conform to each other.

Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.

Abstract: A visible-light-photocatalyzed composite light-transmitting concrete contains several bundles of optical fibers, the optical fibers are coated with a protective layer on their outer surface, the protective layer contains a visible light photocatalyst, and the concrete has several gas-permeable pores. Such concrete is prepared by mixing a visible light photocatalyst and a light-transmitting glue, applying the mixture to the surface of optical fibers to form a protective layer, and using optical fibers in the concrete. The resulting concrete has dual properties of light transmittance and photocatalytic oxidation of gas-phase pollutants under visible light irradiation. The visible-light-photocatalyzed composite light-transmitting concrete significantly breaks through the limitation of photocatalytic concrete to light sources, so that gas-phase pollutants can be removed under visible light irradiation through photocatalysis of light-transmitting concrete.

Abstract: A includes depositing a gate electrode layer over a semiconductor substrate; patterning the gate electrode layer into a first gate electrode and a gate electrode extending portion; forming a first gate spacer alongside the first gate electrode; patterning the gate electrode extending portion into a second gate electrode after forming the first gate spacer; and forming a second gate spacer alongside the second gate electrode and a third gate spacer around the first spacer.

Abstract: An audio transmission device coupled to an electronic device and including a detection circuit, a vendor-defined class circuit, and an audio class circuit is provided. The detection circuit detects an external sound to generate an input voice. The vendor-defined class circuit provides a first voice signal to the electronic device according to the input voice. An audio processing application program of the electronic device processes the first voice signal to generate a processed voice to the vendor-defined class circuit. The audio class circuit receives the processed voice from the vendor-defined class circuit, uses the processed voice as a second voice signal, and provides the second voice signal to the media manager of the electronic device.

Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure, a first gate spacer and a second gate spacer. The first gate spacer includes a first layer, a second layer over the first layer, a third layer over the second layer, a fourth layer over the third layer, and a fifth layer of the fourth layer, in which the first layer, the third layer, and the fifth layer of the first gate spacer are made of a same material. The second gate spacer includes a first layer, a second layer over the first layer, and a third layer over the second layer, in which the first layer and the third layer of the second gate spacer are made of a same material, and in which a lateral width of the first gate spacer is greater than a lateral width of the second gate spacer.

Abstract: Described is an approach for tracking 3D organ motion in real-time using magnetic resonance imaging (MRI). The approach may include offline learning, which may acquire signature and 3D imaging data over multiple respiratory cycles to create a database of high-resolution 3D motion states. The approach may further include online matching, which may acquire signature data only in real-time (latency less than 0.2 seconds). From a motion state and motion signature database, the 3D motion state whose signature best (or sufficiently) matches the newly-acquired signature data may be selected. Real-time 3D motion tracking may be accomplished by performing time-consuming acquisition and reconstruction work in an offline learning phase, leaving just signature acquisition and correlation analysis in an online matching step, minimizing or otherwise reducing latency. The approach may be used to adapt radiotherapy procedures based on tumor motion using a magnetic resonance linear accelerator (MR-Linac) system.

Abstract: Provided is a high-efficiency vanadium nitride/molybdenum carbide heterojunction hydrogen production electrocatalyst, and a preparation method and application thereof. The electrocatalyst has a heterojunction structure formed by coupling VN and Mo2C, wherein the mass ratio of VN and Mo2C is 20:1 to 50:1. The electrocatalyst couples nano-VN and Mo2C to form a VN/Mo2C heterojunction, so that the active center is increased, and the balance of the reaction kinetics of H+ adsorption and H2 desorption is facilitated, thereby greatly improving the activity of the electrocatalyst.

Abstract: Provided is a three-phase system V2O3/VN/Mo2C nanoelectrode material, and a preparation method and application thereof. The nanoelectrode material comprises V2O3 particles, VN particles, and Mo2C particles. The V2O3 particles, VN particles, and Mo2C particles are interlaced in lattice stripes and are uniformly distributed. The mass ratio of the V2O3, VN and Mo2C is (1 to 4):(10 to 40):(4 to 16). The above-mentioned three kinds of nanoparticles are intertwined to form more incoherent interface area. The increase in the area of the incoherent interface area will cause more defects, so that more active sites are provided, and the hydrogen production performance is improved.

Abstract: Various embodiments of the present application are directed to an IC device and associated forming methods. In some embodiments, a memory region and a logic region are integrated in a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices disposed on a plurality of logic sub-regions of the logic region. A first logic device is disposed on a first upper surface of a first logic sub-region. A second logic device is disposed on a second upper surface of a second logic sub-region. A third logic device is disposed on a third upper surface of a third logic sub-region. Heights of the first, second, and third upper surfaces of the logic sub-regions monotonically decrease. By arranging logic devices on multiple recessed positions of the substrate, design flexibility is improved and devices with multiple operation voltages are better suited.

Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Abstract: An approach is provided for domain-specific chatbots that employ distributed natural language classifiers (NLCs). A NLC included in a first chatbot is executed, which generates a first intent of a question and a first confidence that the first intent is an actual intent of the question. Based on a determination that the first confidence does not exceed a threshold, the question is broadcasted to other chatbots. A second confidence that a second intent is an actual intent is received from a second chatbot in response to the broadcast, and is determined to exceed the threshold. An association among the question, the second chatbot, the second confidence, and the second intent is stored in a memory cache included in the first chatbot. A response to the question is generated based on the second intent. The response is presented to a user from the first chatbot.

Abstract: Various embodiments of the present application are directed to a method for forming an integrated circuit (IC), and the associated integrated circuit. In some embodiments, a substrate is provided including a logic region having a plurality of logic sub-regions including a low-voltage logic sub-region and a high-voltage logic sub-region. The method further comprises forming a stack of gate dielectric precursor layers on the plurality of logic sub-regions and removing the stack of gate dielectric precursor layers from the low-voltage logic sub-region and the high-voltage logic sub-region. The method further comprises forming a high-voltage gate dielectric precursor layer on the low-voltage logic sub-region and the high-voltage logic sub-region and removing the high-voltage gate dielectric precursor layer from the low-voltage logic sub-region. The low-voltage logic sub-region has a logic device configured to operate at a voltage smaller than that of another logic device of the high-voltage logic sub-region.

Abstract: Various embodiments of the present application are directed to an IC device and associated forming methods. In some embodiments, a memory region and a logic region are integrated in a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices disposed on a plurality of logic sub-regions of the logic region. A first logic device is disposed on a first upper surface of a first logic sub-region. A second logic device is disposed on a second upper surface of a second logic sub-region. A third logic device is disposed on a third upper surface of a third logic sub-region. Heights of the first, second, and third upper surfaces of the logic sub-regions monotonically decrease. By arranging logic devices on multiple recessed positions of the substrate, design flexibility is improved and devices with multiple operation voltages are better suited.