Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

Abstract: The present invention provides a battery support, and a battery assembly comprising the battery support. The battery support is used to retain a battery assembly having multiple cells; a heat dissipating means of the battery support comprises at least one spacer component, the spacer component has multiple accommodating recesses on at least one side, the accommodating recess is partially shape-fitted to a circumferential sidewall of the cell, and the spacer component is made of a material with a thermal conductivity greater than that of air. The heat dissipating means of the battery support of the present invention is fitted to outer walls of the cells over as large an area as possible, and the heat dissipating means is able to undergo heat exchange with the cells in the process of use of the battery assembly and thus promote heat dissipation from the cells, in order to maintain the efficiency of use and the service life of the battery assembly.

Abstract: A robotic garden tool including a deck, a blade motor configured to rotate a blade about a blade axis, and a mount axially movable with respect to the deck along the blade axis. The garden tool also includes a worm shaft mounted for rotation with respect to the deck about a worm axis, the work shaft forming a threaded interface with the mount such that rotation of the worm shaft about the worm axis causes the mount to move axially with respect to the deck. The garden tool also includes a manual actuator configured to move with respect to the deck in response to receiving a manual actuation force by an operator, where the manual actuator is in operable communication with the worm shaft such that movement of the manual actuator with respect to the deck causes the worm shaft to rotate about the worm axis.

Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure, a first gate spacer and a second gate spacer. The first gate spacer includes a first layer, a second layer over the first layer, a third layer over the second layer, a fourth layer over the third layer, and a fifth layer of the fourth layer, in which the first layer, the third layer, and the fifth layer of the first gate spacer are made of a same material. The second gate spacer includes a first layer, a second layer over the first layer, and a third layer over the second layer, in which the first layer and the third layer of the second gate spacer are made of a same material, and in which a lateral width of the first gate spacer is greater than a lateral width of the second gate spacer.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Abstract: A device for simultaneously measuring mercury, cadmium, zinc, and lead is provided, including: a gas generating device; a quartz analysis tube connected to the gas generating device, and the quartz analysis tube includes a sample heating zone, a high-temperature packing zone and a quartz collimating tube; an atomic absorption detection device AA1 arranged behind the quartz analysis tube, where the atomic absorption detection device includes an atomic absorption detector, a flame, and a light source; a quartz catalytic tube arranged behind the atomic absorption detection device, where the quartz catalytic tube includes a flame buffer zone and an adsorption packing zone; and an atomic absorption mercury measuring device arranged behind the quartz catalytic tube, where the atomic absorption mercury measuring device includes a mercury enrichment tube, an atomic absorption detector AA2 and an air pump.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate. A second dielectric layer is disposed between the floating gate and the control gate, having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof. A third dielectric layer is disposed between the second dielectric layer and the control gate, and includes a dielectric material having a dielectric constant higher than silicon nitride.

Abstract: The invention discloses a fluorescent quantitative PCR technology-based method for distinguishing human DNA, and a fluorescent quantitative PCR technology-based composition or kit for distinguishing human DNA, comprising primers and/or probes of nucleotide sequences.

Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure, a first gate spacer and a second gate spacer. The first gate spacer includes a first layer, a second layer over the first layer, a third layer over the second layer, a fourth layer over the third layer, and a fifth layer of the fourth layer, in which the first layer, the third layer, and the fifth layer of the first gate spacer are made of a same material. The second gate spacer includes a first layer, a second layer over the first layer, and a third layer over the second layer, in which the first layer and the third layer of the second gate spacer are made of a same material, and in which a lateral width of the first gate spacer is greater than a lateral width of the second gate spacer.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) having a first IC structure that includes a first substrate, a first interconnect structure, and a first hybrid bond structure. The second IC structure includes a second substrate and a second hybrid bond structure abutting the first hybrid bond structure at a bond interface. The second substrate includes first and second device regions including first semiconductor devices and second semiconductor devices. The first semiconductor devices being of a first type of IC device and the second semiconductor devices being of a second type of IC device different than the first type of IC device. A bond routing structure couples the first interconnect structure to the first and second semiconductor devices. A lateral routing structure continuously laterally extends from under the first device region to under the second device region.

Abstract: The present disclosure relates integrated chip structure. The integrated chip structure includes one or more interconnects disposed within a dielectric structure over a substrate. A bond pad having a top surface is arranged along a top surface of the dielectric structure. The top surface of the bond pad includes a plurality of discrete top surface segments that are laterally separated from one another by non-zero distances that extend between interior sidewalls of the bond pad, as viewed in a cross-sectional view. The dielectric structure is disposed directly between the interior sidewalls of the bond pad.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Abstract: A device for simultaneously measuring mercury, cadmium, zinc, and lead is provided, including: a gas generating device; a quartz analysis tube connected to the gas generating device, and the quartz analysis tube includes a sample heating zone, a high-temperature packing zone and a quartz collimating tube; an atomic absorption detection device AA1 arranged behind the quartz analysis tube, where the atomic absorption detection device includes an atomic absorption detector, a flame, and a light source; a quartz catalytic tube arranged behind the atomic absorption detection device, where the quartz catalytic tube includes a flame buffer zone and an adsorption packing zone; and an atomic absorption mercury measuring device arranged behind the quartz catalytic tube, where the atomic absorption mercury measuring device includes a mercury enrichment tube, an atomic absorption detector AA2 and an air pump.

Abstract: A stenosis assessment method and device based on the intracranial digital subtraction angiographic (DSA) imaging, including acquiring the intracranial DSA imaging and extracting two planar images containing the target blood vessel from the DSA imaging, wherein the two planar images have different shooting angles. According to the two planar images, a 3D model of the target vessel is established. Based on the established 3D model of the target vessel and the DSA imaging, the hemodynamic simulation of the target vessel is performed. The disclosure realizes the functional assessment of intracranial vascular stenosis, improves the diagnostic accuracy, and provides certain assistance for neurologists to determine intervention means. The disclosure of noninvasive FFR technology in the assessment of intracranial vascular stenosis can only rely on angiography for functional assessment, saving the medical examination cost of patients. It has more convenient operation and higher repeatability.

Abstract: A includes depositing a gate electrode layer over a semiconductor substrate; patterning the gate electrode layer into a first gate electrode and a gate electrode extending portion; forming a first gate spacer alongside the first gate electrode; patterning the gate electrode extending portion into a second gate electrode after forming the first gate spacer; and forming a second gate spacer alongside the second gate electrode and a third gate spacer around the first spacer.

Abstract: A semiconductor device includes a substrate, an isolation structure, a conductive structure, and a first contact structure. The isolation structure is disposed in the substrate. The conductive structure is disposed on the isolation structure. The conductive structure extends upwards from the isolation structure, in which the first contact structure has a top portion on the conductive structure and a bottom portion in contact with the isolation structure.