Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.

Abstract: Provided is a photocurable conductive black composition including: (a) at least one (meth)acrylate-functionalized urethane oligomer; (b) at least one photopolymerizable compound; (c) a photoinitiator; (d) a visible-light blocking system; (e) conductive fillers; and optionally (f) a thermal initiator. Also provided are a method for forming a cured product composed of the photocurable conductive black compositions, and an article comprising the cured product.

Abstract: An interconnect structure on a semiconductor die includes: a lower conductive layer; an upper conductive layer disposed above the lower conductive layer; and a VIA disposed between the lower conductive layer and the upper conductive layer. The VIA includes: a primary interconnect structure and a sacrificial stress barrier ring disposed around the primary interconnect structure and separated a distance from the primary interconnect structure. A fabrication method for the interconnect structure includes: forming a dielectric layer over a lower conductive layer; patterning photoresist (PR) layer over the dielectric layer to define a location for a plurality of VIA trenches, wherein the patterning includes patterning the PR layer to provide a center opening for the VIA trenches that is surrounded by a ring opening for the VIA trenches, wherein the center opening and the ring opening are spaced apart.

Abstract: A separator for a lithium battery and a method for manufacturing the same are provided. The separator includes a substrate layer and a coating layer. The substrate layer is a polyolefin porous film and has a substrate thickness ranging from 10 to 30 micrometers. The coating layer is coated on the substrate layer, and has a coating layer thickness ranging from 1 to 5 micrometers. The coating layer includes a heat-resistant resin material and a plurality of inorganic ceramic particles glued in the heat-resistant resin material. The heat-resistant resin material has a melting point (Tm) or a glass transition temperature (Tg) of not less than 150° C. An average particle size of the inorganic ceramic particles is 10% to 40% of the coating layer thickness of the coating layer. The inorganic ceramic particles are stacked in the coating layer with a height of at least three layers.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.

Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Abstract: A tool set includes a tool holder, a tool and a tool rack. The tool has a groove unit. The tool holder has a latch unit that engages the groove unit. The tool rack includes a rack body and a blocking member. When the tool holder is moved away from the rack body after the tool is moved into the rack body by the tool holder and after the blocking member moves to a blocking position, the tool is blocked by the blocking member so that the latch unit is separated from the groove unit and that the tool holder is separated from the tool.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: A behavior recognition device for recognizing behaviors of a semiconductor manufacturing apparatus includes a storage device and a control unit. The storage device is configured to store log data of the semiconductor manufacturing apparatus. The control unit is cooperatively connected to the storage device, and configured to build a transition state model based on the log data to analyze behaviors related to wafer transfer sequences and manufacturing operations of the semiconductor manufacturing apparatus.

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments isolation regions are formed by modifying a dielectric material of a dielectric layer such that a first portion of the dielectric layer is more readily removed by an etching process than a second portion of the dielectric layer. The modifying of the dielectric material facilitates subsequent processing steps that allow for the tuning of a profile of the isolation regions to a desired geometry based on the different material properties of the modified dielectric material.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: A semiconductor structure includes two source/drain features spaced apart from each other, at least one channel feature disposed between the two source/drain features, a gate dielectric layer disposed on the at least one channel feature, a gate feature, and an electrically conductive capping feature. The gate feature is disposed on the gate dielectric layer and has a first surface, a second surface which is opposite to the first surface, and an interconnect surface which interconnects the first and second surfaces. The electrically conductive capping feature is in direct contact with one of the first and second surfaces of the gate feature, and extends beyond the interconnect surface of the gate feature. Methods for manufacturing the semiconductor structure are also disclosed.

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: Provided is a device including a fin structure and methods for forming such a device. A method includes forming an initial fin having a sidewall. Further, the method includes forming an additional layer of fin material over the sidewall, wherein the additional layer has a thickness. Also, the method includes adjusting the thickness of the additional layer of fin material to form a fin structure with a desired critical dimension.

Abstract: A method for manufacturing a semiconductor device includes: forming a patterned structure on a substrate, the patterned structure including a dielectric layer and a dummy gate structure disposed in the dielectric layer; and subjecting the patterned structure to an ion implantation process so as to modulate a profile of the dummy gate structure.

Abstract: In an embodiment, an apparatus includes a first pyrometer and a second pyrometer configured to monitor thermal radiation from a first point and a second point on a backside of a wafer, respectively, a first heating source in a first region and a second heating source in a second region of an epitaxial growth chamber, respectively, where a first controller adjusts an output of the first heating source and the second heating source based upon the monitored thermal radiation from the first point and the second point, respectively, a third pyrometer and a fourth pyrometer configured to monitor thermal radiation from a third point and a fourth point on a frontside of the wafer, respectively, where a second controller adjusts a flow rate of one or more precursors injected into the epitaxial growth chamber based upon the monitored thermal radiation from the first, second, third, and fourth points.

Abstract: An intensity of a power laser beam applied to a semiconductor device is adjusted. An applied intensity of the power laser beam is indicative of a magnitude at which the power laser beam is emitted toward the semiconductor device and a reflection intensity of a probing laser beam applied to the semiconductor device is indicative of an emissivity of the semiconductor device. The reflection intensity of the probing laser beam is measured to determine the emissivity of the semiconductor device and the applied intensity of the power laser beam is adjusted as a function of the emissivity.

Abstract: A method of forming a semiconductor device includes removing a light-sensitive material from a workpiece utilizing polarized electromagnetic radiation and annealing features on the workpiece utilizing electromagnetic radiation polarized in a different direction than the polarized electromagnetic radiation utilized to remove the light-sensitive material. In some embodiments, the electromagnetic radiation used to anneal the features on the workpiece is not polarized. In some described embodiments, light-sensitive material removed from the workpiece is exhausted from the chamber in which the light-sensitive removal process is carried out before it can deposit on surfaces of the chamber.