Patents by Inventor Li TING

Li TING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230387251
    Abstract: A method for manufacturing a semiconductor device includes: forming a patterned structure on a substrate, the patterned structure including a dielectric layer and a dummy gate structure disposed in the dielectric layer; and subjecting the patterned structure to an ion implantation process so as to modulate a profile of the dummy gate structure.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tien-Shun CHANG, Kuo-Ju CHEN, Sih-Jie LIU, Wei-Fu WANG, Yi-Chao WANG, Li-Ting WANG, Su-Hao LIU, Huicheng CHANG, Yee-Chia YEO
  • Publication number: 20230383435
    Abstract: In an embodiment, an apparatus includes a first pyrometer and a second pyrometer configured to monitor thermal radiation from a first point and a second point on a backside of a wafer, respectively, a first heating source in a first region and a second heating source in a second region of an epitaxial growth chamber, respectively, where a first controller adjusts an output of the first heating source and the second heating source based upon the monitored thermal radiation from the first point and the second point, respectively, a third pyrometer and a fourth pyrometer configured to monitor thermal radiation from a third point and a fourth point on a frontside of the wafer, respectively, where a second controller adjusts a flow rate of one or more precursors injected into the epitaxial growth chamber based upon the monitored thermal radiation from the first, second, third, and fourth points.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Li-Ting Wang, Jung-Jen Chen, Ming-Hua Yu, Yee-Chia Yeo
  • Publication number: 20230377915
    Abstract: An intensity of a power laser beam applied to a semiconductor device is adjusted. An applied intensity of the power laser beam is indicative of a magnitude at which the power laser beam is emitted toward the semiconductor device and a reflection intensity of a probing laser beam applied to the semiconductor device is indicative of an emissivity of the semiconductor device. The reflection intensity of the probing laser beam is measured to determine the emissivity of the semiconductor device and the applied intensity of the power laser beam is adjusted as a function of the emissivity.
    Type: Application
    Filed: May 17, 2022
    Publication date: November 23, 2023
    Inventors: Wei-Fu Wang, Yi-Chao Yi-Chao, Li-Ting Wang, Yee-Chia Yeo
  • Publication number: 20230377884
    Abstract: A method of forming a semiconductor device includes removing a light-sensitive material from a workpiece utilizing polarized electromagnetic radiation and annealing features on the workpiece utilizing electromagnetic radiation polarized in a different direction than the polarized electromagnetic radiation utilized to remove the light-sensitive material. In some embodiments, the electromagnetic radiation used to anneal the features on the workpiece is not polarized. In some described embodiments, light-sensitive material removed from the workpiece is exhausted from the chamber in which the light-sensitive removal process is carried out before it can deposit on surfaces of the chamber.
    Type: Application
    Filed: May 19, 2022
    Publication date: November 23, 2023
    Inventors: Tz-Shian CHEN, Li-Ting WANG, Yee-Chia YEO
  • Publication number: 20230364300
    Abstract: The present application relates to use of transglutaminases to treat various products, including medical devices such as tissue grafts, tissue matrices or other tissue-derived materials, and synthetics. The transglutaminases can be applied to the medical devices to provide advantages such as adhesion resistance or abrasion resistance.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Inventors: Yi Chen, Sean Collins, Li Ting Huang, Eric Stec, Hui Xu
  • Patent number: 11800857
    Abstract: A liver lesion-mouse model which is a liver-specific ISX gene expression and p53 gene knockout transgenic mouse, wherein liver lesion develops after the mouse is fed with a high calorie diet.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: October 31, 2023
    Assignee: Kaohsiung Medical University
    Inventors: Shih-Hsien Hsu, Li-Ting Wang, Shen-Nien Wang, Kwei-Yan Liu
  • Publication number: 20230282706
    Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 7, 2023
    Inventors: Wei-Ting Chien, Wen-Yen Chen, Li-Ting Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang
  • Patent number: 11724004
    Abstract: The present application relates to use of transglutaminases to treat various products, including medical devices such as tissue grafts, tissue matrices or other tissue-derived materials, and synthetics. The transglutaminases can be applied to the medical devices to provide advantages such as adhesion resistance or abrasion resistance.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: August 15, 2023
    Assignee: LifeCell Corporation
    Inventors: Yi Chen, Sean Collins, Li Ting Huang, Eric Stec, Hui Xu
  • Publication number: 20230253470
    Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Inventors: Chi-Sheng Lai, Yu-Fan Peng, Li-Ting Chen, Yu-Shan Lu, Yu-Bey Wu, Wei-Chung Sun, Yuan-Ching Peng, Kuei-Yu Kao, Shih-Yao Lin, Chih-Han Lin, Pei-Yi Liu, Jing Yi Yan
  • Publication number: 20230238594
    Abstract: A lithium battery system is provided. The lithium battery system comprises a battery pack, a battery management module, and a cooling control module. The battery pack comprises a first battery module and a second battery module having different battery characteristics. The battery management module is electrically connected to the battery pack, and configured to control an operating condition of the battery pack according to the battery characteristics of the first battery module and the second battery module. The cooling control module is electrically connected to the battery management module and the battery pack, and configured to cool the battery pack according to an instruction of the battery management module. The application combines a variety of lithium batteries with different performances to obtain a lithium battery system with excellent comprehensive performance.
    Type: Application
    Filed: December 21, 2022
    Publication date: July 27, 2023
    Inventors: CHUN-HSIEN CHO, KUO-CHIH YU, LI-TING CAI
  • Publication number: 20230215758
    Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.
    Type: Application
    Filed: March 13, 2023
    Publication date: July 6, 2023
    Inventors: Wen-Yen Chen, Li-Ting Wang, Wan-Chen Hsieh, Bo-Cyuan Lu, Tai-Chun Huang, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11695042
    Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: July 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Ting Chien, Wen-Yen Chen, Li-Ting Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang
  • Publication number: 20230197852
    Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.
    Type: Application
    Filed: February 24, 2023
    Publication date: June 22, 2023
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
  • Patent number: 11652003
    Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Sheng Lai, Wei-Chung Sun, Li-Ting Chen, Kuei-Yu Kao, Chih-Han Lin
  • Patent number: 11631745
    Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Sheng Lai, Yu-Fan Peng, Li-Ting Chen, Yu-Shan Lu, Yu-Bey Wu, Wei-Chung Sun, Yuan-Ching Peng, Kuei-Yu Kao, Shih-Yao Lin, Chih-Han Lin, Pei-Yi Liu, Jing Yi Yan
  • Publication number: 20230114216
    Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin structure on a substrate. The fin structure includes a plurality of first nanostructures and a plurality of second nanostructures alternately stacked. A dummy gate is formed along sidewalls and a top surface of the fin structure. A portion of the fin structure exposed by the dummy gate is recessed to form a first recess. An epitaxial source/drain region is formed in the first recess. Dopant atoms within the epitaxial source/drain region are driven into the plurality of second nanostructures. The dummy gate and the plurality of first nanostructures are removed. A replacement gate is formed wrapping around the plurality of second nanostructures.
    Type: Application
    Filed: May 13, 2022
    Publication date: April 13, 2023
    Inventors: Yi-Yun Li, Tsai-Yu Huang, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11615761
    Abstract: A calibration method for splicing displays including initializing a plurality of displays, obtaining the gamuts of the displays, setting a display with the smallest gamut among the displays as the reference display, adjusting the color temperature, brightness and six-axis hue and saturation of the reference display respectively to a reference color temperature, a reference brightness and reference RGB coordinates, and adjusting the displays according to the reference color temperature, the reference brightness and the reference RGB coordinates.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: March 28, 2023
    Assignees: BenQ Intelligent Technology (Shanghai) Co., Ltd, BENQ CORPORATION
    Inventors: Li-Ting Tsai, Yi-Ho Bai
  • Patent number: 11605635
    Abstract: In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: March 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Ying Chen, Sen-Hong Syue, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11605555
    Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: March 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Yen Chen, Li-Ting Wang, Wan-Chen Hsieh, Bo-Cyuan Lu, Tai-Chun Huang, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20230061802
    Abstract: A method of manufacturing a semiconductor device includes: determining a first reflectivity of a first anneal region on a wafer; determining a second reflectivity of a second anneal region on the wafer, performing a first laser shot on the first anneal region, measuring a first temperature of the first anneal region, and performing a second laser shot on a second anneal region. A power of the first laser shot is set in accordance with the first reflectivity. A power of the second laser shot is set in accordance with the second reflectivity.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Tz-Shian Chen, Li-Ting Wang, Yee-Chia Yeo