Abstract: A method is described herein of making a textured glass article, the method includes: etching an initial primary surface of a glass substrate having a thickness with a hydrofluoric acid-free etchant having a pH of about 3 or less; and removing the etchant from the glass substrate, such that the etching is conducted from above ambient temperature to about 100° C. to form a textured region that is defined by a primary surface of the substrate and comprises a sparkle of 2% or less, and the etching comprises a plurality of batch cycles.

Abstract: A circuit module with reliable margin configuration, may include a main circuit, a first auxiliary circuit and a second auxiliary circuit. When the first auxiliary circuit is on, the second auxiliary circuit may be on or off according to whether a control signal is of a first level or a second level. When the first auxiliary circuit and the second auxiliary circuit are both on, the first auxiliary circuit and the second auxiliary circuit may jointly cause an operation parameter of the main circuit to be a first value. When the first auxiliary circuit is on and the second auxiliary circuit is off, the first auxiliary circuit may cause the operation parameter to be a second value. An operation margin of the main circuit may cover a range between the first value and the second value.

Abstract: An electronic device of an embodiment of the disclosure includes a first substrate, a second substrate, and a driving layer. The first substrate and the second substrate are disposed opposite to each other, and the driving layer is disposed between the first substrate and the second substrate. The driving layer includes a scan line and a data line. The scan line is disposed on the first substrate and includes a first scan line segment. The first scan line segment has an opening and includes a first branch and a second branch. The first branch and the second branch are located on two opposite sides of the opening and are electrically connected in parallel with each other. The data line is disposed on the first substrate and intersects with the scan line. The electronic device of the embodiment of the disclosure may exhibit ideal display effect.

Abstract: A viewing angle control element and a display module are provided. The viewing angle control element includes a first substrate, a plurality of first spacer units, a plurality of second spacer units, and a second substrate. The plurality of first spacer units are disposed on the first substrate. The plurality of second spacer units are respectively disposed on the plurality of first spacer units. The second substrate is disposed on the plurality of second spacer units. A reflectivity of the plurality of first spacer units is greater than a reflectivity of the plurality of second spacer units.

Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit o discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.

Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a first resistance-capacitance (RC) timer circuit, a second RC timer circuit, a voltage pull-down circuit, a voltage pull-up circuit, a discharge circuit, and a discharge control circuit. The first RC timer circuit is coupled between a first power supply voltage and a reference voltage. The second RC timer circuit is coupled between a second power supply voltage and the reference voltage. The voltage pull-up circuit is coupled between the second power supply voltage and the reference voltage through a first resistor. The discharge circuit is coupled between the second power supply voltage and the reference voltage. The discharge control circuit is coupled between a third node and the reference voltage, and controls the discharge circuit using a first voltage generated by the first RC timer circuit.

Abstract: A display module is provided, which includes a display device, a first viewing-angle control device and a second viewing-angle control device. The first viewing-angle control device includes a first substrate, a second substrate, a first liquid-crystal layer and a first transparent conductive layer. The first transparent conductive layer is disposed between the first substrate and the second substrate and includes a first portion. The second viewing-angle control device includes a third substrate, a fourth substrate, a second liquid-crystal layer and a second transparent conductive layer. The second transparent conductive layer is disposed between the third substrate and the fourth substrate and includes a second portion, and the second portion overlaps the first portion. In a cross-sectional view, a side of the first portion of the first transparent conductive layer is separated from a side of the second portion of the second transparent conductive layer by a first distance.

Abstract: A thin film transistor substrate includes a substrate, a first metal layer disposed on the substrate, a second metal layer disposed on the first metal layer, a semiconductor disposed between the substrate and the first metal layer, and a first insulating layer disposed between the first metal layer and the second metal layer. The first metal layer includes a gate pattern, the second metal layer includes a scan line pattern, the semiconductor includes an active region, and the first insulating layer includes a first opening. The gate pattern overlaps the active region, and the scan line pattern of the second metal layer is electrically connected to the gate pattern of the first metal layer through the first opening in the first insulating layer.

Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.

Abstract: An electronic device is provided and includes a substrate, a first bump, a second bump, and an electronic element. The substrate includes a first through hole and a second through hole disposed adjacent to the first through hole along a direction. The first bump and the second bump are overlapped with the substrate, wherein the first bump is adjacent to the second bump along the direction. The electronic element is overlapped with the substrate and electrically connected to the first bump, wherein the substrate is disposed between the first bump and the electronic element. A distance between the first through hole and the second through hole of the substrate along the direction is different from a distance between the first bump and the second bump along the direction.

Abstract: A dynamic random access memory device includes a substrate having a first active region, a first isolation region, a second active region, and a second isolation region arranged in order along a first direction. A first bit line is disposed on the first active region and in direct contact with the first active region. A second bit line is disposed on the second isolation region. An insulating layer is disposed between and separate the second bit line and the second isolation region. A storage node contact structure is disposed between the first bit line and the second bit line and is in direct contact with a top surface of the second active region, a sidewall of the first isolation region, and a sidewall of the second isolation region.

Abstract: A semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode with the second cathode connected to a first supply voltage. The semiconductor device includes a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input/output pin, with the third anode connected to a second supply voltage. The second anode is coupled to a circuit that is powered by the first supply voltage and the second supply voltage. The first diode has a first size and the second diode has a second size, and the first size is substantially greater than the second size.

Abstract: A frequency locked loop circuit, comprising an operational circuit, a first impedance circuit, a second impedance circuit, a switching circuit and a frequency generation circuit. The operational circuit is configured to output an operational signal according to a voltage difference between a positive terminal and a negative terminal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node. The frequency generation circuit is configured to periodically sample the operational signal to generate a sample signal to generate a clock signal. An operational frequency of the operational signal is an integer multiple of a sampling frequency of the frequency generation circuit.

Abstract: The present application relates to a biochemical reaction test strip tube and a use method thereof, and a kit. The biochemical reaction test strip tube includes a tube portion and a cover portion. The tube portion includes: a tube body including a first chamber and a second chamber; a limit unit provided at an outer side of the tube body; and a biochemical chromatographic test strip provided inside the second chamber, where a first end of the biochemical chromatographic test strip is provided with a sample absorption pad. In this structure, different chambers are provided in the closed test tube, such that a biochemical reaction solution in one chamber is directly detected on the biochemical chromatographic test strip in another chamber, which avoids the solution leakage; and different chambers are provided at different heights, such that the chambers holding biochemical reaction reagents can be selectively heated.

Abstract: A display device has a transmissive area and a reflective area. The transmissive area corresponds to a first sub-pixel, and the reflective area corresponds to a second sub-pixel. The display device includes a backlight module, a liquid crystal module, and an anti-reflective layer. The liquid crystal module is disposed on the backlight module and includes a first substrate, a component layer, and a reflective layer. The component layer is disposed on the first substrate and includes a first transistor and a second transistor. The first transistor is configured to drive the first sub-pixel, and the second transistor is configured to drive the second sub-pixel. The reflective layer is disposed on the component layer and corresponds to the reflective area. The anti-reflective layer is disposed on the liquid crystal module.

Abstract: The disclosure provides a light emitting device including a substrate and a plurality of sub-pixels disposed on the substrate. The plurality of sub-pixels include a first sub-pixel of a first color, a second sub-pixel of a second color different from the first color, and a third sub-pixel of the second color, wherein the first sub-pixel is disposed adjacent to the second sub-pixel, and the first sub-pixel is disposed adjacent to the third sub-pixel, and wherein a width of the second sub-pixel along a first direction is different from a width of the third sub-pixel along the first direction.

Abstract: A circuit module with improved timing control, may comprise a functional circuit, a control circuit, a main auxiliary circuit and an additional auxiliary circuit. The control circuit may control operation timing of the functional circuit according to response characteristics of a first node. When enabled, the main auxiliary circuit may provide main conduction path(s) between the first node and a base node. Respectively when enabled and disabled, the additional auxiliary circuit may provide and not provide additional conduction path(s) between the first node and the base node. When the control circuit controls the operation timing of the functional circuit, the main auxiliary circuit may be enabled, and the additional auxiliary circuit may be disabled or enabled according to whether a mode signal is of a first mode level or a second level.

Abstract: A multi-tactile feedback component is suitable for an electronic device and includes a thin film deformation element, a thin film vibration element, and a power module. The thin film deformation element has first and second elastic layers and a gain layer disposed therebetween and forming a channel to accommodate a fluid. The thin film vibration element is connected to the thin film deformation element and has a piezoelectric layer and tactile structures. The tactile structures are disposed at a side surface of the piezoelectric layer. The power module is coupled to the thin film deformation element and the thin film vibration element. When the power module supplies an electrical energy to the thin film deformation element, the first elastic layer is deformed to push the fluid and the second elastic layer. When the power module supplies the electrical energy to the thin film vibration element, the piezoelectric layer vibrates.

Abstract: An electronic device includes a surface structure. The surface structure has a curved surface and includes a substrate, a first conductive line, and a first dielectric pattern. The first conductive line is disposed above the substrate. The first dielectric pattern is disposed above the first conductive line and overlaps with the first conductive line. The surface structure has a first region and a second region. The first dielectric pattern in the first region has a first average width, the first dielectric pattern in the second region has a second average width, and the first average width is different from the second average width.