Patents by Inventor Li Wei
Li Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088179Abstract: A chip packaging structure and a chip packaging method are provided. The chip packaging structure includes a first substrate, an image sensing chip, a supporting member, a second substrate, and an encapsulant. The image sensing chip is disposed on an upper surface of the first substrate, and the image sensing chip has an image sensing region. The supporting member is disposed on an upper surface of the image sensing chip and surrounds the image sensing region. The supporting member is formed by stacking microstructures with each other, so that the supporting member has pores. The second substrate is disposed on an upper surface of the supporting member, and the second substrate, the supporting member, and the image sensing chip define an air cavity. The encapsulant is attached to the upper surface of the first substrate and a side surface of the second substrate and filled into the pores.Type: ApplicationFiled: October 18, 2022Publication date: March 14, 2024Applicant: TONG HSING ELECTRONIC INDUSTRIES, LTD.Inventors: You-Wei Chang, Chien-Chen Lee, Li-Chun Hung
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Patent number: 11929322Abstract: Device, package structure and method of forming the same are disclosed. The device includes a die encapsulated by an encapsulant, a conductive structure aside the die, and a dielectric layer overlying the conductive structure. The conductive structure includes a through via in the encapsulant, a redistribution line layer overlying the through via, and a seed layer overlying the redistribution line layer. The dielectric layer includes an opening, wherein the opening exposes a surface of the conductive structure, the opening has a scallop sidewall, and an included angle between a bottom surface of the dielectric layer and a sidewall of the opening is larger than about 60 degrees.Type: GrantFiled: July 25, 2022Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, An-Jhih Su, Li-Hsien Huang
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Patent number: 11929547Abstract: A mobile device includes a system circuit board, a metal frame, one or more other antenna elements, a display device, a first feeding element, and an RF (Radio Frequency) module. The system circuit board includes a system ground plane. The metal frame at least includes a first portion and a second portion. The metal frame at least has a first cut point positioned between the first portion and the second portion. The metal frame further has a second cut point for separating the other antenna elements from the first portion. The first cut point is arranged to be close to a middle region of the display device. The first feeding element is directly or indirectly electrically connected to the first portion. A first antenna structure is formed by the first feeding element and the first portion.Type: GrantFiled: April 7, 2023Date of Patent: March 12, 2024Assignee: HTC CorporationInventors: Tiao-Hsing Tsai, Chien-Pin Chiu, Hsiao-Wei Wu, Li-Yuan Fang, Shen-Fu Tzeng, Yi-Hsiang Kung
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Patent number: 11929363Abstract: In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.Type: GrantFiled: March 21, 2022Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Lin Peng, Li-Wei Chu, Ming-Fu Tsai, Jam-Wem Lee, Yu-Ti Su
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Patent number: 11926833Abstract: The present disclosure relates to a transgenic plant cell comprising polynucleotide sequences encoding glycolate dehydrogenase, malate synthase, and an inhibitory polynucleotide targeting an endogenous glycolate transporter Plgg1, wherein expression of endogenous glycolate transporter Plgg1 in the transgenic plant cell is about 20% to 80% of expression of endogenous glycolate transporter Plgg1 in a plant cell that is not transformed with an inhibitory polynucleotide targeting an endogenous glycolate transporter Plgg1. Also disclosed are transgenic plants, transgenic plant cultures, and methods for increasing photosynthesis efficiency in plants. The disclosed methods enhance biomass productivity and reduce the negative impact of photorespiration and introduction of transgenic constructs on plant growth.Type: GrantFiled: January 12, 2023Date of Patent: March 12, 2024Assignee: LIVING CARBON PBCInventors: Madeline Hall, Li-Wei Chiu, Rebecca Dewhirst, Jacob Hoyle, Patrick Mellor, Karli Rasmussen, Yumin Tao
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Publication number: 20240076417Abstract: The present disclosure provides a method for manufacturing an auto-crosslinked hyaluronic acid gel, comprising conducting auto-crosslinking reaction of a colloid containing hyaluronic acid continuously at low temperature in an acidic environment, and treating the reaction product with steam at high temperature to obtain the auto-crosslinked hyaluronic acid gel with high viscosity.Type: ApplicationFiled: September 5, 2023Publication date: March 7, 2024Applicant: SCIVISION BIOTECH INC.Inventors: TAI-SHIEN HAN, TSUNG-WEI PAN, TOR-CHERN CHEN, CHUN-CHANG CHEN, PO-HSUAN LIN, LI-SU CHEN
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Publication number: 20240078979Abstract: An electronic device including a display device is provided. The display device includes a sharing area, a junction area, and a privacy area. The junction area is positioned between the sharing area and the privacy area. The display device includes a privacy panel. A transmittance of the privacy panel corresponding to the sharing area is greater than a transmittance of the privacy panel corresponding to the junction area, and the transmittance of the privacy panel corresponding to the junction area is greater than a transmittance of the privacy panel corresponding to the privacy area.Type: ApplicationFiled: August 8, 2023Publication date: March 7, 2024Applicants: Innolux Corporation, CARUX TECHNOLOGY PTE. LTD.Inventors: Li-Wei Sung, Chia-Hsien Lin, Cheng-Wu Lin, Yu-Ming Wu
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Publication number: 20240079399Abstract: A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.Type: ApplicationFiled: November 13, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chien Pan, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
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Patent number: 11923259Abstract: A package structure includes a package substrate, a first semiconductor package and a second semiconductor package, an underfill material, a gap filling structure and a heat dissipation structure. The first semiconductor package and the second semiconductor package are electrically bonded to the package substrate. The underfill material is disposed to fill a first space between the first semiconductor package and the package substrate and a second space between the second semiconductor package and the package substrate. The gap filling structure is disposed over the package substrate and in a first gap laterally between the first semiconductor package and the second semiconductor package. The heat dissipation structure is disposed on the package substrate and attached to the first semiconductor package and the second semiconductor package through a thermal conductive layer.Type: GrantFiled: November 11, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pu Wang, Li-Hui Cheng, Szu-Wei Lu, Tsung-Fu Tsai
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Publication number: 20240072170Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Yih-Ann Lin, Chia Ming Liang, Ryan Chia-Jen CHEN
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Publication number: 20240069660Abstract: An electronic device and a forming method thereof are provided. The electronic device includes a substrate, a metal layer, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer. The metal layer is disposed on the substrate and includes a sensing line and a drain electrode. The first insulating layer is disposed on the metal layer. The first conductive layer is disposed on the first insulating layer and includes a touch electrode. The second insulating layer is disposed on the first conductive layer. The second conductive layer is disposed on the second insulating layer and includes a conductive pattern. The conductive pattern is electrically connected to the sensing line and the touch electrode.Type: ApplicationFiled: July 18, 2023Publication date: February 29, 2024Inventors: Kuei-Chen CHIU, Yu-Ti HUANG, Cheng-Tso CHEN, Li-Wei SUNG
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Publication number: 20240071849Abstract: A semiconductor package including one or more dam structures and the method of forming are provided. A semiconductor package may include an interposer, a semiconductor die bonded to a first side of the interposer, an encapsulant on the first side of the interposer encircling the semiconductor die, a substrate bonded to the a second side of the interposer, an underfill between the interposer and the substrate, and one or more of dam structures on the substrate. The one or more dam structures may be disposed adjacent respective corners of the interposer and may be in direct contact with the underfill. The coefficient of thermal expansion of the one or more of dam structures may be smaller than the coefficient of thermal expansion of the underfill.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Inventors: Jian-You Chen, Kuan-Yu Huang, Li-Chung Kuo, Chen-Hsuan Tsai, Kung-Chen Yeh, Hsien-Ju Tsou, Ying-Ching Shih, Szu-Wei Lu
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Publication number: 20240071947Abstract: A semiconductor package including a ring structure with one or more indents and a method of forming are provided. The semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. The ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. The first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Inventors: Yu-Ling Tsai, Lai Wei Chih, Meng-Tsan Lee, Hung-Pin Chang, Li-Han Hsu, Chien-Chia Chiu, Cheng-Hung Lin
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Publication number: 20240070109Abstract: The present disclosure provides an USB device and a system type determining method thereof. The system type determining method includes: determining, by the USB device, whether an USB host transmit at least one of an HID interrupt signal and an UAC1 status interrupt signal; and determining, by the USB device, a system type of the USB host according to the result of determining whether the USB host transmit at least one of the HID interrupt signal and the UAC1 status interrupt signal.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Inventors: PO-CHAO HUANG, LI-WEI HUANG
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Patent number: 11915976Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.Type: GrantFiled: June 27, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Chu, Ying-Chi Su, Yu-Kai Chen, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang, Ming-Hsing Tsai
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Patent number: 11916074Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.Type: GrantFiled: July 27, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Wei Peng, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Li-Chun Tien, Pin-Dai Sue, Wei-Cheng Lin
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Publication number: 20240062731Abstract: An electronic device includes a display panel, a backlight source, an ambient light sensor, and a controller. The backlight source is disposed below the display panel and includes light-emitting units. The ambient light sensor detects the brightness of the ambient light. The controller judges the modes of the electronic device according to the detecting results of the ambient light sensor. When the electronic device is in a low-brightness mode, the brightness of a white frame of the display panel is greater than 0 nit and less than or equal to 50 nits, and in a general mode, the brightness of the white frame of the display panel is greater than 50 nits. The backlight source includes a local dimming function. When in the low-brightness mode, the local dimming function is in a first mode. When in the general mode, the local dimming function is in a second mode.Type: ApplicationFiled: July 18, 2023Publication date: February 22, 2024Inventors: Chao-Chin SUNG, Hsin-Cheng HUNG, Chien-Tzu CHU, Li-Wei SUNG
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Patent number: 11908742Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a semiconductor substrate, a first fin and a second fin extending from the semiconductor substrate, a first lower semiconductor feature over the first fin, a second lower semiconductor feature over the second fin. Each of the first and second lower semiconductor features includes a top surface bending downward towards the semiconductor substrate in a cross-sectional plane perpendicular to a lengthwise direction of the first and second fins. The semiconductor device also includes an upper semiconductor feature over and in physical contact with the first and second lower semiconductor features, and a dielectric layer on sidewalls of the first and second lower semiconductor features.Type: GrantFiled: June 14, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jing Lee, Jeng-Wei Yu, Li-Wei Chou, Tsz-Mei Kwok, Ming-Hua Yu
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Patent number: D1017096Type: GrantFiled: June 26, 2023Date of Patent: March 5, 2024Inventors: Dongwei Ge, Zhiyuan Yu, Cheng Zhang, Li Wei
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Patent number: D1017101Type: GrantFiled: August 17, 2022Date of Patent: March 5, 2024Inventors: Dongwei Ge, Li Wei, Cheng Zhang