Patents by Inventor Li Wei

Li Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250040039
    Abstract: A package assembly includes a substrate, an electronic component and a cover. The electronic component and the cover are disposed on the substrate, wherein the electronic component is located within a chamber between the cover and the substrate. A cooling liquid may be filled in a heat dissipation space of the cover, so as to dissipate the heat generated by the electronic component. Furthermore, the cooling liquid may be filled in the chamber where the electronic component is located, so as to directly dissipate the heat generated by the electronic component.
    Type: Application
    Filed: October 10, 2024
    Publication date: January 30, 2025
    Applicant: Wiwynn Corporation
    Inventors: Yi Cheng, Wei-Ching Chang, Kang-Bin Mah, Li-Wei Chen, Zi-Ping Wu, Ting-Yu Pai
  • Publication number: 20250038524
    Abstract: Devices, circuits, and methods for electrostatic discharge (ESD) protection are provided. An electrostatic discharge (ESD) protection circuit comprises a first transistor connected between a first voltage and a second voltage, and a first control circuit connected between the first voltage and the second voltage, and configured to supply a control signal to the first transistor. The circuit further comprises a second transistor connected between the second voltage and a third voltage, and a second control circuit connected between the second voltage and the third voltage, and configured to supply a control signal to the second transistor. The first control circuit and the second control circuit are connected to each other via a first interconnect and a second interconnect. The first and second transistors are configured to turn on in response to an ESD event.
    Type: Application
    Filed: July 26, 2023
    Publication date: January 30, 2025
    Inventors: Jam-Wem Lee, Wun-Jie Lin, Chia-Jung Chang, Li-Wei Chu
  • Patent number: 12211570
    Abstract: A test circuit coupled to a memory device and configured to read data stored in the memory device during a memory dump, includes a dump controller and a pattern generator. The dump controller triggers the pattern generator to start a pattern generating operation in response to a setting of memory dump mode by a processor. The pattern generator generates multiple control signals in the pattern generating operation and provides the control signals to the memory device. The control signals include an address signal, a memory enable signal and a read enable signal. The address signal includes multiple memory addresses arranged in multiple consecutive clock cycles of the processor. The consecutive clock cycles of the processor is provided to read the data stored in the memory addresses.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: January 28, 2025
    Assignee: Realtek Semiconductor Corp.
    Inventors: Li-Wei Deng, Ying-Yen Chen, Chih-Tung Chen
  • Publication number: 20250029547
    Abstract: An electronic device and a driving method for an electronic device are provided. The electronic device includes a sensor, a controller, a driving circuit, and at least one electronic unit. The sensor senses an ambient temperature to provide ambient temperature information. The controller receives the ambient temperature information. The driving circuit drives the at least one electronic unit according to a driving signal. The driving circuit generates different driving signals according to different ambient temperature information.
    Type: Application
    Filed: June 5, 2024
    Publication date: January 23, 2025
    Applicants: Innolux Corporation, CARUX TECHNOLOGY PTE. LTD.
    Inventors: Yi-Cheng Chang, Chung-Le Chen, Li-Wei Sung
  • Patent number: 12205501
    Abstract: The present disclosure provides an electronic device including a substrate, a plurality of bumps, a plurality of diodes, and a shielding layer. The substrate has a plurality of first through holes. The bumps are disposed on the substrate. The diodes are disposed on the substrate. The shielding layer is disposed on the substrate. One of the bumps is located between two adjacent ones of the diodes in a cross-sectional view, and the shielding layer overlaps at least a portion of the bumps and at least a portion of the first through holes.
    Type: Grant
    Filed: May 22, 2024
    Date of Patent: January 21, 2025
    Assignee: InnoLux Corporation
    Inventors: Chin-Lung Ting, Chung-Kuang Wei, Li-Wei Mao, Chi-Liang Chang, Chia-Hui Lin
  • Publication number: 20250024663
    Abstract: According to one or more embodiments of the disclosure, a method comprises: forming a first recess for a bit line contact structure of a semiconductor device; providing a liner on a surface of the first recess; etching the linear to open at least part of a bottom of the liner, forming a second recess under the first recess; performing an epitaxial growth process through the second recess; and providing a conductive material to the first and second recesses to form at least part of the bit line contact structure.
    Type: Application
    Filed: June 19, 2024
    Publication date: January 16, 2025
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Vivek Yadav, Li Wei Fang
  • Publication number: 20250024608
    Abstract: A circuit structure is provided. The circuit structure includes an insulating layer, a conductive pad and a solder pad. The insulating layer has a first surface and a second surface opposite to the first surface. The conductive pad is disposed on the first surface of the insulating layer. The solder pad is disposed on the second surface of the insulating layer. The solder pad is coupled to the conductive pad. The insulating layer has a recess region on the second surface.
    Type: Application
    Filed: October 1, 2024
    Publication date: January 16, 2025
    Applicant: Innolux Corporation
    Inventors: Yi Hung Lin, Li-Wei Sung
  • Publication number: 20250019777
    Abstract: The invention relates to isolation, purification, and in vitro cultivation of Symbiodinium algae symbiotic with soft corals. The deposit information for Symbiodinium sp. SY-1 is as follows: Depository Name: China General Microbiological Culture Collection Center (CGMCC); Depository Address: Institute of Microbiology, Chinese Academy of Sciences, Building 3, No. 1 Beichen West Road, Chaoyang District, Beijing, China; Deposit Date: Jun. 7, 2023; Deposit Number: CGMCC No. 40681; Taxonomy: Symbiodinium sp.
    Type: Application
    Filed: July 26, 2024
    Publication date: January 16, 2025
    Applicant: Hainan Normal University
    Inventors: Li WEI, Meng FENG, Han ZHU, Rong WANG, Xiangchen GAO, Jiecan YU
  • Patent number: 12196522
    Abstract: High pressure compressed gas pressure vessels and devices utilizing such vessels are disclosed herein. More particularly, aspects of the present invention are directed to high pressure (i.e., nitrogen or N2 based) pressurized gas cylinders with pierceable membranes recessed from the opening of the pressure vessel such that prior art piercing mechanisms cannot pierce the membrane for safety purposes. Additionally, aspects of the present invention are directed to pressurized gas operated devices with elongated pins for piercing pressure vessels with recessed pierceable membranes.
    Type: Grant
    Filed: July 18, 2024
    Date of Patent: January 14, 2025
    Assignee: BANZA STAMPING INDUSTRY CORPORATION
    Inventors: Li-Wei Chen, Tsang-Yao Lu, Min-Yan Xie
  • Patent number: 12200923
    Abstract: The present disclosure relates to a method of fabricating a semiconductor device, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: January 14, 2025
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Li-Wei Feng, Yu-Cheng Tung
  • Patent number: 12191655
    Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.
    Type: Grant
    Filed: November 20, 2023
    Date of Patent: January 7, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Wei Chu, Tao Yi Hung, Chia-Hui Chen, Wun-Jie Lin, Jam-Wem Lee
  • Publication number: 20250006716
    Abstract: A display device including a display module and a backlight module is provided. The display module has a display region. The backlight module is overlapped with the display module and includes a plurality of light emitting diodes. The plurality of light emitting diodes form a light emitting region. The light emitting region is overlapped with the display region, and an area of the light emitting region is larger than an area of the display region.
    Type: Application
    Filed: May 17, 2024
    Publication date: January 2, 2025
    Applicant: CARUX TECHNOLOGY PTE. LTD.
    Inventors: Shun-Yu Chang, Wei-Hsuan Lee, Li-Wei Sung, Zhi-Wei Lin
  • Publication number: 20250001248
    Abstract: A rehabilitation device is adapted for wrist rehabilitation, and includes two magnetic actuators and a movable frame unit. Each of the magnetic actuator includes a motor, a rotating shaft, a rotating member, and two magnetic coupling subunits that are respectively connected to the motor and the rotating shaft. Each of the magnetic coupling subunits includes a magnetic ring that has a plurality of N pole portions and a plurality of S pole portions alternately arranged about a center of the magnetic ring. For each of the magnetic actuators, when one of the magnetic coupling subunits that is connected to the motor is driven by the motor to rotate, the other one of the magnetic coupling subunits that is connected to the rotating shaft is urged to rotate by attraction between the magnetic rings of the magnetic coupling subunits such that the rotating shaft and the rotating member rotate.
    Type: Application
    Filed: August 23, 2023
    Publication date: January 2, 2025
    Applicant: National Tsing Hua University
    Inventors: Li-Wei CHENG, Zhi-Yong CHEN, Jen-Yuan CHANG
  • Patent number: 12185608
    Abstract: The disclosure provides a light emitting device including a substrate and multiple pixels. The pixels are disposed on the substrate, each of the pixels includes multiple sub-pixels. Two adjacent sub-pixels are separated by a distance D, and one of the two adjacent sub-pixels has a height H. The distance and the height satisfy a relational expression: 0.3H<D?30H.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: December 31, 2024
    Assignee: Innolux Corporation
    Inventors: Li-Wei Mao, Ker-Yih Kao, Ming-Chia Shih
  • Publication number: 20240429922
    Abstract: A synchronization signal generation circuit and a synchronization method among a plurality of devices are proposed. The synchronization signal generation circuit includes a clock signal generator and a controller. The clock signal generator generates a reference clock signal. The controller receives an input clock signal from a host end device and generates a plurality of candidate clock signals through a plurality of counting operations based on the reference clock signal. The controller selectively transmits one of the candidate clock signals to each peripheral device according to request information corresponding to each peripheral device. The candidate clock signals and the input clock signal have mutually aligned start time points in each frame period.
    Type: Application
    Filed: February 5, 2024
    Publication date: December 26, 2024
    Applicant: HTC Corporation
    Inventors: Sheng-Long Wu, Wei-Chih Kuo, Shih-Yao Tsai, Li-Wei Lin, Chao Shuan Huang
  • Publication number: 20240429358
    Abstract: An electronic device is provided. The electronic device includes a first substrate and a plurality of light-emitting elements disposed on the first substrate. The plurality of light-emitting elements include a contact pad; an intermediate substrate disposed on the contact pad; and a light-emitting unit disposed on the intermediate substrate. The electronic device further includes a second substrate and a first thin-film transistor array disposed on the second substrate for driving at least a portion of the plurality of light-emitting elements. The light-emitting unit is electrically connected to the contact pad through a via hole that penetrates the intermediate substrate.
    Type: Application
    Filed: February 1, 2024
    Publication date: December 26, 2024
    Inventors: Shun-Yuan HU, Chin-Lung TING, Ker-Yih KAO, Li-Wei MAO, Kung-Chen KUO, Yi-Hua HSU, Ming-Chun TSENG
  • Patent number: 12175152
    Abstract: An image display method and a control system are provided. A processor is configured to split an original image into multiple sub-images and then output the sub-images to multiple corresponding displays to respectively display. Process of splitting the original image includes: finding multiple regions of interest (ROIs) in the original image to generate a ROI matrix; using a mask to perform a specified operation on each pixel of the original image to obtain a priority matrix; performing gradient calculation on each pixel of the original image to generate a gradient matrix; generating an integration matrix based on the ROI matrix, the priority matrix and the gradient matrix; determining a splitting path based on the integration matrix; and splitting the original image into multiple sub-images based on the splitting path.
    Type: Grant
    Filed: March 20, 2024
    Date of Patent: December 24, 2024
    Assignee: Wistron Corporation
    Inventors: Li Wei Chen, Chin Hao Hsu, Hui-Chen Lin, Ming Chiuan Jing
  • Publication number: 20240418475
    Abstract: High pressure compressed gas pressure vessels and devices utilizing such vessels are disclosed herein. More particularly, aspects of the present invention are directed to high pressure (i.e., nitrogen or N2 based) pressurized gas cylinders with pierceable membranes recessed from the opening of the pressure vessel such that prior art piercing mechanisms cannot pierce the membrane for safety purposes. Additionally, aspects of the present invention are directed to pressurized gas operated devices with elongated pins for piercing pressure vessels with recessed pierceable membranes.
    Type: Application
    Filed: May 16, 2024
    Publication date: December 19, 2024
    Inventors: Li-Wei Chen, Tsang-Yao LU, Min-Yan XIE
  • Publication number: 20240422958
    Abstract: A semiconductor device which includes a substrate, storage node pads, a capacitor structure and a supporting structure, and a forming method thereof are disclosed. The substrate includes a cell region and a periphery region. The storage node pads are disposed on the substrate and located in the cell region. The capacitor structure is disposed on the storage node pads and includes bottom electrodes in contact with the storage node pads. The supporting structure is disposed on the storage node pads and interleaved among the bottom electrodes. The supporting structure includes a first supporting layer and a second supporting layer sequentially from bottom to top. The second supporting layer includes a first thickness and a second thickness, wherein the second thickness is greater than the first thickness, and the second supporting layer with the second thickness is disposed between the cell region and the periphery region to provide improved structural support.
    Type: Application
    Filed: August 23, 2023
    Publication date: December 19, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Li-Wei Feng
  • Publication number: 20240418476
    Abstract: High pressure compressed gas pressure vessels and devices utilizing such vessels are disclosed herein. More particularly, aspects of the present invention are directed to high pressure (i.e., nitrogen or N2 based) pressurized gas cylinders with pierceable membranes recessed from the opening of the pressure vessel such that prior art piercing mechanisms cannot pierce the membrane for safety purposes. Additionally, aspects of the present invention are directed to pressurized gas operated devices with elongated pins for piercing pressure vessels with recessed pierceable membranes.
    Type: Application
    Filed: July 18, 2024
    Publication date: December 19, 2024
    Inventors: Li-Wei Chen, Tsang-Yao LU, Min-Yan XIE