Patents by Inventor Li-Wen Wang
Li-Wen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096630Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.Type: ApplicationFiled: January 12, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Jih-Sheng Yang, Shih-Chieh Chao, Yih-Ann Lin, Ryan Chia-Jen Chen
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Publication number: 20240072170Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Yih-Ann Lin, Chia Ming Liang, Ryan Chia-Jen CHEN
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Publication number: 20240046979Abstract: A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells; each of the bit cells being coupled correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including local write drivers correspondingly coupled to the segments; and a global write driver coupled to each of the local write drivers.Type: ApplicationFiled: October 6, 2023Publication date: February 8, 2024Inventors: Hidehiro FUJIWARA, Hung-Jen LIAO, Li-Wen WANG, Jonathan Tsung-Yung CHANG, Yen-Huei CHEN
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Patent number: 11783890Abstract: A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells that are connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver and local write drivers included correspondingly in the segments; and the global write driver including a first equalizer circuit, arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line, and the global write driver and the local write drivers each including first inversion couplings (coupled in parallel between the GWB line and the LWB line) and second inversion couplings (coupled in parallel between the GWB_bar line and the LWB_bar line).Type: GrantFiled: July 29, 2022Date of Patent: October 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen
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Publication number: 20220366965Abstract: A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells that are connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver and local write drivers included correspondingly in the segments; and the global write driver including a first equalizer circuit, arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line, and the global write driver and the local write drivers each including first inversion couplings (coupled in parallel between the GWB line and the LWB line) and second inversion couplings (coupled in parallel between the GWB_bar line and the LWB_bar line).Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Inventors: Hidehiro FUJIWARA, Hung-Jen LIAO, Li-Wen WANG, Jonathan Tsung-Yung CHANG, Yen-Huei CHEN
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Patent number: 11468543Abstract: A neural network receives mono-color pixels in a Bayer pattern from an image sensor and interpolates pixels to generate full-color RGB pixels while also enlightening the image for better detail. A Back-Projection (BP) layer is added to each contracting layer in a U-net convolution neural network where feature depth is increased as pixels are downsampled, while a BP channel shrink layer is added to each expansion layer where feature depth is reduced to upsample and increase pixel resolution. Convolution layers in the BP layer lighten and darken images to generate an error that is then lightened and added to a weighted lightened input. The neural network learns the best weightings to correct for noise and error in the lightening process in these BP layers. Noise is reduced further by repeating a convolution and leaky Rectified Linear Unit (lrelu) in series for the first convolution in the BP layer that performs lightening.Type: GrantFiled: August 27, 2021Date of Patent: October 11, 2022Assignee: Hong Kong Applied Science and Technology Research Institute Company LimitedInventors: Li-Wen Wang, Wan-Chi Siu, Zhi-Song Liu, Yan Huo, Xingbo Guan, Miaohui Hao
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Patent number: 11423974Abstract: A method of fabricating (a distributed write driving arrangement for a semiconductor memory device) includes: forming bit cells and a local write driver in a first device layer; forming a local write bit (LWB) line and a local write bit_bar (LWB_bar) line in a first metallization layer; connecting each of the bit cells correspondingly between the LWB and LWB_bar lines; connecting the local write driver to the LWB line and the LWB_bar line; forming a global write bit (GWB) line and a global write bit_bar (GWBL_bar) line in a second metallization layer; connecting the GWB line to the LWB line; connecting the GWB line and the GWBL_bar line to the corresponding LWB line and LWB_bar line; forming a global write driver in a second device layer; and connecting the global write driver to the GWB line and the GWBL_bar line.Type: GrantFiled: April 27, 2021Date of Patent: August 23, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen
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Patent number: 11152301Abstract: A method of designing a memory circuit is provided that includes generating a layout of a first memory cell using an integrated circuit design system. The layout of the first memory cell is generated by routing a first word line in a first layer on a first level, and routing a second word line in the first layer. Also, the method includes generating a layout of a second memory cell using the integrated circuit design system. The layout of the second memory cell is generated by routing a third word line in the first layer, the second word line being between the first word line and the third word line, and routing a fourth word line in the first layer, the third word line being between the second word line and the fourth word line. Moreover, the method includes assigning a first color scheme to the first word line and to the third word line, and assigning a second color scheme to the second word line and to the fourth word line.Type: GrantFiled: July 15, 2019Date of Patent: October 19, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Hung-Jen Liao
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Patent number: 11120868Abstract: A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.Type: GrantFiled: December 5, 2019Date of Patent: September 14, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Yuan Chen, Che-Ju Yeh, Hau-Tai Shieh, Cheng Hung Lee, Hung-Jen Liao, Sahil Preet Singh, Manish Arora, Hemant Patel, Li-Wen Wang
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Publication number: 20210280437Abstract: A method of fabricating (a distributed write driving arrangement for a semiconductor memory device) includes: forming bit cells and a local write driver in a first device layer; forming a local write bit (LWB) line and a local write bit_bar (LWB_bar) line in a first metallization layer; connecting each of the bit cells correspondingly between the LWB and LWB_bar lines; connecting the local write driver to the LWB line and the LWB_bar line; forming a global write bit (GWB) line and a global write bit_bar (GWBL_bar) line in a second metallization layer; connecting the GWB line to the LWB line; connecting the GWB line and the GWBL_bar line to the corresponding LWB line and LWB_bar line; forming a global write driver in a second device layer; and connecting the global write driver to the GWB line and the GWBL_bar line.Type: ApplicationFiled: April 27, 2021Publication date: September 9, 2021Inventors: Hidehiro FUJIWARA, Hung-Jen LIAO, Li-Wen WANG, Jonathan Tsung-Yung CHANG, Yen-Huei CHEN
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Patent number: 10991420Abstract: A semiconductor memory device includes: a column of segments, each segment including bit cells; a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; each of the bit cells being connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and a local write driver included in each segment, each local write driver being connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and wherein: the global write driver and each local write driver is connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line.Type: GrantFiled: August 12, 2020Date of Patent: April 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen
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Patent number: 10905653Abstract: Provided is a sequentially decomposable polypeptide-based nanocarrier with protective shell for delivery of hydrophobic drugs and preparation thereof.Type: GrantFiled: October 21, 2016Date of Patent: February 2, 2021Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Li-Wen Wang, Tzu-Wei Wang
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Publication number: 20200372950Abstract: A semiconductor memory device includes: a column of segments, each segment including bit cells; a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; each of the bit cells being connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and a local write driver included in each segment, each local write driver being connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and wherein: the global write driver and each local write driver is connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line.Type: ApplicationFiled: August 12, 2020Publication date: November 26, 2020Inventors: Hidehiro FUJIWARA, Hung-Jen LIAO, Li-Wen WANG, Jonathan Tsung-Yung CHANG, Yen-Huei CHEN
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Patent number: 10783955Abstract: A circuit includes a column of memory cells, a first read data line coupled exclusively with a first subset of memory cells of the column of memory cells, a second read data line coupled exclusively with a second subset of memory cells of the column of memory cells, and a plurality of read word lines. Each read word line of the plurality of read word lines is coupled with a memory cell of the first subset of memory cells and with a memory cell of the second subset of memory cells.Type: GrantFiled: November 30, 2018Date of Patent: September 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Hung-Jen Liao
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Patent number: 10755768Abstract: A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells; each of the bit cells including a latch circuit and first and second pass gates connecting the corresponding LWB and LWB_bar lines to the latch circuit; and a distributed write driving arrangement. The distributed write driving arrangement includes: a global write driver including a first inverter connected between the GWB line and the LWB line, and a second inverter connected between the GWB_bar line and the LWB_bar line; and a local write driver included at an interior of each segment, each local write driver including a third inverter connected between the GWB line and the LWB line; and a fourth inverter connected between the GWB_bar line and the LWB_bar line.Type: GrantFiled: July 3, 2019Date of Patent: August 25, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen
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Patent number: 10651114Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.Type: GrantFiled: December 18, 2018Date of Patent: May 12, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Yu Lin, Kao-Cheng Lin, Li-Wen Wang, Yen-Huei Chen
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Publication number: 20200111526Abstract: A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Inventors: Chien-Yuan Chen, Che-Ju Yeh, Hau-Tai Shieh, Cheng-Hung Lee, Hung-Jen Liao, Sahil Preet Singh, Manish Arora, Hemant Patel, Li-Wen Wang
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Publication number: 20200020383Abstract: A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells; each of the bit cells including a latch circuit and first and second pass gates connecting the corresponding LWB and LWB_bar lines to the latch circuit; and a distributed write driving arrangement. The distributed write driving arrangement includes: a global write driver including a first inverter connected between the GWB line and the LWB line, and a second inverter connected between the GWB_bar line and the LWB_bar line; and a local write driver included at an interior of each segment, each local write driver including a third inverter connected between the GWB line and the LWB line; and a fourth inverter connected between the GWB_bar line and the LWB_bar line.Type: ApplicationFiled: July 3, 2019Publication date: January 16, 2020Inventors: Hidehiro FUJIWARA, Hung-Jen LIAO, Li-Wen WANG, Jonathan Tsung-Yung CHANG, Yen-Huei CHEN
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Patent number: 10510401Abstract: A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.Type: GrantFiled: May 16, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semicondutor Manufacturing Company LimitedInventors: Chien-Yuan Chen, Che-Ju Yeh, Hau-Tai Shieh, Cheng-Hung Lee, Hung-Jen Liao, Sahil Preet Singh, Manish Arora, Hemant Patel, Li-Wen Wang
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Publication number: 20190341346Abstract: A method of designing a memory circuit is provided that includes generating a layout of a first memory cell using an integrated circuit design system. The layout of the first memory cell is generated by routing a first word line in a first layer on a first level, and routing a second word line in the first layer. Also, the method includes generating a layout of a second memory cell using the integrated circuit design system. The layout of the second memory cell is generated by routing a third word line in the first layer, the second word line being between the first word line and the third word line, and routing a fourth word line in the first layer, the third word line being between the second word line and the fourth word line. Moreover, the method includes assigning a first color scheme to the first word line and to the third word line, and assigning a second color scheme to the second word line and to the fourth word line.Type: ApplicationFiled: July 15, 2019Publication date: November 7, 2019Inventors: Hidehiro FUJIWARA, Li-Wen WANG, Yen-Huei CHEN, Hung-Jen LIAO