Abstract: A circuit includes a first circuit configured to sense a leakage of a first bit line and output a first signal in response, and a second circuit configured to receive the first signal output from the first circuit and in response supply current to a second bit line for maintaining a voltage level of the second bit line.

Abstract: A method of manufacturing a transflective liquid crystal display panel includes the following steps. A substrate is provided. A first patterned conductive layer is formed on the substrate to form a gate electrode and a reflective electrode. A first insulating layer is formed on the first patterned conductive layer and the substrate. A patterned semiconductor layer is formed on the first insulating layer. A second patterned conductive layer is formed on the first insulating layer and the patterned semiconductor layer to form a source/drain electrode and a patterned reflective layer. A second insulating layer is formed on the second patterned conductive layer and the first insulating layer. Contact holes are formed in the first and the second insulating layer. A transmissive pixel electrode is formed and filled into the contact holes to be electrically connected respectively to the drain electrode, the reflective electrode, and the patterned reflective layer.

Abstract: A method includes a) receiving a design for a static random access memory (SRAM) array including an SRAM cell having a read port cell, the read port cell including first and second MOS transistors each having an initial threshold voltage (Vth); b) adjusting one of a gate channel width (Wg) or a gate channel length (Lg) of one of the first and second MOS transistors to modify the Vth of at least one of the first and second MOS transistors; c) simulating a response of the SRAM array, the simulation providing response data for the SRAM array including the Vth for the first and second MOS transistors; and d) iteratively repeating steps b) and c) until a desired Vth is achieved.

Abstract: A method of fabricating a pixel array substrate is disclosed. The reflective pixel array substrate can be made by utilizing five photo masks only. The reflective pixel array substrate includes a substrate, a thin film transistor, a reflective electrode, an insulating layer and numerous protruding bumps. The step between the protrusion bump and the substrate cause the reflective electrode thereon to have a corrugated structure. The gate electrode of the thin film transistor and the protruding bumps are made of a same conductive layer. The drain electrode connects the reflective electrode, and the drain electrode and the reflective electrode are made of a same conductive layer.

Abstract: A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed.

Abstract: Apparatus and methods for providing SRAM timing tracking cell circuits are disclosed. In an embodiment, an apparatus comprises an SRAM array comprising static random access memory cells arranged in rows and columns; a plurality of word lines each coupled to memory cells along one of the rows; a clock generation circuit for outputting clock signals; a word line generation circuit for generating a pulse on the plurality of word lines responsive to one of the clock signals and for ending the pulse responsive to one of the clock signals; and a tracking cell for receiving a clock signal and for outputting a word line pulse end signal to the clock generation circuit, following an SRAM tracking time; wherein the tracking cell further comprises SRAM tracking circuits positioned in the SRAM array and coupled in series to provide a signal indicating the SRAM tracking time. Methods for SRAM timing are disclosed.

Abstract: A transflective liquid crystal display panel includes a substrate, a gate electrode, a reflective electrode, a first insulating layer, a patterned semiconductor layer, a source electrode, a drain electrode, a patterned reflective layer, a second insulating layer, and at least a transmissive pixel electrode. The gate electrode and the reflective electrode are both formed by a first patterned conductive layer, and the source electrode, the drain electrode, and the patterned reflective layer are both formed by a second patterned conductive layer. Furthermore, a plurality of contact holes are formed in the first insulating layer and the second insulating layer. Moreover, the transmissive pixel electrode is filled into the contact holes to be electrically connected with the drain electrode, the reflective electrode, and the patterned reflective layer, respectively.

Abstract: A method of manufacturing a transflective liquid crystal display panel includes the following steps. A substrate is provided. A first patterned conductive layer is formed on the substrate to form a gate electrode and a reflective electrode. A first insulating layer is formed on the first patterned conductive layer and the substrate. A patterned semiconductor layer is formed on the first insulating layer. A second patterned conductive layer is formed on the first insulating layer and the patterned semiconductor layer to form a source/drain electrode and a patterned reflective layer. A second insulating layer is formed on the second patterned conductive layer and the first insulating layer. Contact holes are formed in the first and the second insulating layer. A transmissive pixel electrode is formed and filled into the contact holes to be electrically connected respectively to the drain electrode, the reflective electrode, and the patterned reflective layer.

Abstract: A pixel array substrate is disclosed. The reflective pixel array substrate can be made by utilizing five photo masks only. The reflective pixel array substrate includes a substrate, a thin film transistor, a reflective electrode, an insulating layer and numerous protruding bumps. The step between the protrusion bump and the substrate cause the reflective electrode thereon to have a corrugated structure. The gate electrode of the thin film transistor and the protruding bumps are made of a same conductive layer. The drain electrode connects the reflective electrode, and the drain electrode and the reflective electrode are made of a same conductive layer.

Abstract: A method of fabricating a pixel array substrate is disclosed. The reflective pixel array substrate can be made by utilizing five photo masks only. The reflective pixel array substrate includes a substrate, a thin film transistor, a reflective electrode, an insulating layer and numerous protruding bumps. The step between the protrusion bump and the substrate cause the reflective electrode thereon to have a corrugated structure. The gate electrode of the thin film transistor and the protruding bumps are made of a same conductive layer. The drain electrode connects the reflective electrode, and the drain electrode and the reflective electrode are made of a same conductive layer.

Abstract: The invention relates to the use of an enzyme preparation which catalyzes the degradation of formaldehyde for reducing the formaldehyde content in a formaldehyde-containing formulation. In a preferred embodiment, the enzyme preparation contains a formaldehyde dismutase from a Pseudomonas putida strain. Further, the invention refers to a process for reducing the formaldehyde content in cross-linking agents for textile finishing or in polymer dispersions used, e.g. in construction chemistry. Further the invention relates to the use of an enzyme preparation which catalyzes the degradation of aldehydes for reducing the formaldehyde content in an aldehyde-containing formulation. Furthermore, the invention relates to a novel variant of the formaldehyde dismutase from Pseudomonas putida.

Abstract: An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.

Abstract: A method includes a) receiving a design for a static random access memory (SRAM) array including an SRAM cell having a read port cell, the read port cell including first and second MOS transistors each having an initial threshold voltage (Vth); b) adjusting one of a gate channel width (Wg) or a gate channel length (Lg) of one of the first and second MOS transistors to modify the Vth of at least one of the first and second MOS transistors; c) simulating a response of the SRAM array, the simulation providing response data for the SRAM array including the Vth for the first and second MOS transistors; and d) iteratively repeating steps b) and c) until a desired Vth is achieved.

Abstract: A compound of the following formula: in which R1, R2, R3, U, V, T, W, X, Y, Z, m, n, p, x, y, and z are as defined herein. Also disclosed are (1) a pharmaceutical composition containing such a compound, and (2) a method for treating Hepatitis C virus infection using such a compound.

Abstract: Imidazolidinone and imidazolinethione compounds of formula (I): wherein R1, R2, R3, A1, A2, X, Y, Z, m, n, p, x, and y are defined herein. Also disclosed is a method of treating hepatitis C virus infection with these compounds.

Abstract: Thiourea compounds of the following formula: wherein n, R1, R2, R3, A1, A2, X, Y, and Z are defined herein. Also disclosed is a method of treating hepatitis C virus infection with these compounds.

Abstract: An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.

Abstract: An adaptor mount is provided for use with a gun having a Picatiny rail. A first accessory may be mounted on a first portion of the Picatiny rail of the gun. The adaptor mount has a clamp, and a mount piece having a body and a platform that, together with the clamp, defines a receiving space. The adaptor mount further includes an auxiliary Picatiny rail extending transverse to the body of the mount, with a second accessory mounted on the auxiliary Picatiny rail. A fixing screw extends through the auxiliary Picatiny rail, the body, the receiving space and the clamp, and a locking nut is positioned adjacent the clamp and engaged to the fixing screw. A second portion of the Picatiny rail of the gun is received inside the receiving space to secure the adaptor mount to the Picatiny rail of the gun.

Abstract: Imidazolidinone and imidazolinethione compounds of formula (I): wherein R1, R2, R3, A1, A2, X, Y, Z, m, n, p, x, and y are defined herein. Also disclosed is a method of treating hepatitis C virus infection with these compounds.

Abstract: Thiourea compounds of the following formula: wherein n, R1, R2, R3, A1, A2, X, Y, and Z are defined herein. Also disclosed is a method of treating hepatitis C virus infection with these compounds.