Abstract: A circuit comprises a memory array, a tracking bit line and a timing control circuit. The memory array comprises a plurality of tracking cells. The tracking bit line is coupled between a first node and the plurality of tracking cells. The timing control circuit is coupled to the first node and comprises a Schmitt trigger. The Schmitt trigger generates a negative bit line enable signal in response to that a voltage level on the first node being below a low threshold voltage value of the Schmitt trigger. The timing control circuit generates a negative bit line trigger signal according to the negative bit line enable signal for adjusting voltage levels of a plurality of bit lines of the memory array.

Abstract: A method, apparatus, and computer instructions stored on a computer-readable medium perform latent image feature extraction by performing the functions of receiving image data acquired during an imaging of a patient, wherein the image data includes motion by the patient during the imaging; segmenting the image data to include M image data segments corresponding to at least N motion phases having shorter durations than a duration of the motion by the patient during the imaging, wherein M is a positive integer greater than or equal to a positive integer N; producing, from the M image data segments, at least N latent feature vectors corresponding to the motion by the patient during the imaging; and performing a gated reconstruction of the N motion phases by reconstructing the image data based on the at least N latent feature vectors.

Abstract: The present invention provides a valve material having a long-acting antithrombosis property and a preparation method therefor. The preparation method therefor comprises the following steps: performing glutaraldehyde cross-linking treatment on an animal-derived biological valve material, so that the valve material can resist decomposition for a long time; soaking the treated valve material in a formulation solution containing a cross-linking agent and a modifier for 10-60 min, then increasing the temperature to 30-60° C., and performing heat treatment for 1-12 h; and rinsing the valve material after heat treatment, so as to obtain the valve material. The valve material prepared by the method has excellent antithrombosis and anti-calcification properties, and can effectively solve the problem of calcification and thrombosis in the valve material treated by existing means of glutaraldehyde cross-linking.

Abstract: The present disclosure generally relates to vacuum generation devices.

Abstract: This invention proposes a single-vector-based finite control set model predictive control for two parallel power converters, which adopts a centralized control structure to achieve accurate control of overall performance. It establishes predictive models for line currents and three phase-circulating currents and constructs a novel cost function that uses these currents as performance indices to implement the predictive control algorithm based on the proposed predictive models. The invention proposes dynamic weighting coefficients and adjustment principles to improve system control performance. A finite set output signal matrix containing important characteristic information of all alternative vectors is constructed to avoid redundant calculations in each control horizon, reducing computation time during practical implementation.

Abstract: A method of forming an LMNO cathode with electrolytic manganese dioxide includes dissolving metallic manganese in acid to create a dissolved manganese solution, disposing the solution within an electrolytic cell including an electrolytic cell anode and an electrolytic cell cathode, and applying a current between the cell anode and the cell cathode to the solution. Applying the current forms an MnO2 deposit upon the cell anode. The method further includes harvesting the deposit, creating a manganese precursor by neutralizing the deposit and grinding the deposit to form an MnO2 powder, and mixing the manganese precursor with a nickel precursor and a lithium precursor to create a mixture. The method further includes calcining the mixture to create an LMNO powder and coating a current collector with the LMNO powder to thereby form the LMNO cathode. The method may include testing the cathode electrode in an electrochemical pouch format cell.

Abstract: Dynamic additive attention adaption for memory-efficient multi-domain on-device learning is provided. Almost all conventional methods for multi-domain learning in deep neural networks (DNNs) only focus on improving accuracy with minimal parameter update, while ignoring high computing and memory cost during training. This makes it difficult to deploy multi-domain learning into resource-limited edge devices, like mobile phones, internet-of-things (IoT) devices, embedded systems, and so on. To reduce training memory usage, while keeping the domain adaption accuracy performance, Dynamic Additive Attention Adaption (DA3) is proposed as a novel memory-efficient on-device multi-domain learning approach. Embodiments of DA3 learn a novel additive attention adaptor module, while freezing the weights of the pre-trained backbone model for each domain.

Abstract: Provided are a digital-to-analog conversion circuit and method. The digital-to-analog conversion circuit includes a conversion unit and a first regulating unit. The conversion unit includes a first code value receiving terminal used to receive a first code value, and the conversion unit is used to convert the first code value into an analog signal. The first regulating unit includes a second code value receiving terminal used to receive a second code value. A signal input terminal of the first regulating unit is connected to a signal output terminal of the conversion unit. The first regulating unit is used to acquire a first analog regulation signal according to the second code value, and regulate, by using the first analog regulation signal, an analog signal transmitted by the conversion unit.

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

Abstract: A long-acting super-hydrophobic anticoagulant biological valve and a preparation method therefor. The preparation method includes the following steps: (1) treating a biological valve material with glutaraldehyde; (2) placing the biological valve material treated in step (1) into an acid liquid containing a polyphenol compound and metal ions, and adding an oxidant for reaction; and (3) reacting the biological valve material treated in step (2) with a hydrophobic substance. According to the method, a super-hydrophobic coating having a long-acting high water contact angle and a low rolling angle is prepared on the surface of the biological valve by means of a simple and stable operation process without affecting the performance of the valve body, and the requirements of long-acting anticoagulation are met by resisting the adsorption of plasma proteins.

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

Abstract: Bifidobacterium animalis and application of a compound bacterium preparation prepared from the Bifidobacterium animalis in the preparation of a medicine for treating or preventing avian influenza virus infection. The invention discovers that Bifidobacterium animalis ATCC Accession No. 25527 can be used for treating animals infected by H7N9, and after the Bifidobacterium animalis ATCC Accession No. 25527 is compounded with Bifidobacterium pseudolongum ATCC Accession No. 25526, the effect is better. The compound preparation can regulate the body immune response, remarkably improve the weight loss and lung tissue injury caused by H7N9 influenza virus infection, and obviously improve the survival rate of mice infected by H7N9 influenza virus. The compound probiotic preparation provided by the invention has a remarkable effect of resisting H7N9 influenza virus infection, and can be effectively used for preventing and treating avian influenza virus infection.

Abstract: Provided is a friction nano power generation synaptic transistor. The friction nano power generation synaptic transistor includes a friction nano generator, a synaptic transistor, a substrate, an electrode layer formed on the substrate, a shared intermediate layer formed on the electrode layer; a synaptic transistor active layer, a source electrode, and a drain electrode which are formed on the shared intermediate layer; and a positive friction layer and a negative friction layer formed on the shared intermediate layer, where the shared intermediate layer is used as a dielectric layer of the synaptic transistor and an intermediate layer of the friction nano generator.

Abstract: A semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate, a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, a seal ring structure including first and second interconnect structures, and a passivation layer on the seal ring structure and the second dielectric layer. The first interconnect structure is located in the first dielectric layer. The second interconnect structure is located in the second dielectric layer and connected to the first interconnect structure. The passivation layer has a spacer portion covering a sidewall of the second dielectric layer and a portion of the first dielectric layer. A ditch exists in the passivation layer and the first dielectric layer. The spacer portion is located between the ditch and the seal ring structure. The semiconductor structure is able to reduce time and power of an etching process for forming the ditch.

Abstract: A memory device includes a memory array, a first latch and a first logic element. The memory array is configured to operate according to a first global write signal. The first latch is configured to generate a first latch write data based on a clock signal. The first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.

Abstract: A method for object grasping, including: determining features of a scene; determining candidate grasp locations; determining a set of candidate grasp proposals for the candidate grasp locations; optionally modifying a candidate grasp proposal of the set; determining grasp scores associated with the candidate grasp proposals; selecting a set of final grasp proposals based on the grasp scores; and executing a grasp proposal from the set of final grasp proposals.

Abstract: An example of a negative electrode includes silicon nanoparticles having a carbon coating thereon. The carbon coating has an oxygen-free structure including pentagon rings. The negative electrode with the silicon nanoparticles having the carbon coating thereon may be incorporated into a lithium-based battery. In an example of a method, silicon nanoparticles are provided. A carbon precursor is applied on the silicon nanoparticles. The carbon precursor is an oxygen-free, fluorene-based polymer. Then the silicon nanoparticles are heated in an inert gas atmosphere to form the carbon coating on the silicon nanoparticles. The carbon coating formed on the silicon nanoparticles has an oxygen-free structure including pentagon rings.

Abstract: The present disclosure describes methods, system, and devices for negotiating minimization of drive test (MDT) parameters of user equipment (UE). One method includes receiving, by a radio access network (RAN) node, a first message from a core network (CN) or an operation and maintain system (OAM), the first message comprising at least one of a negotiable or a non-negotiable MDT configuration parameter; in response to receiving the first message, determining whether the UE is suitable to carry out a MDT task corresponding to the first message; in response to the determining that the UE is suitable to carry out the MDT task corresponding to the first message, sending a second message to the UE; receiving a third message from the UE, the third message comprising at least a value suggested by the UE for the negotiable MDT configuration parameter; and sending a fourth message to the CN or the OAM.

Abstract: The present disclosure describes methods, system, and devices for configuring a user equipment (UE) for minimization of drive test (MDT). One method includes receiving, by a radio access network (RAN) node, a start message from a core network (CN) or an operation and maintain system (OAM). The start message comprising at least one MDT configuration item and optional non-access stratum (NAS) information, the at least one MDT configuration item comprising at least one of the following MDT configuration information: an expected position, an expected mobility profile, an expected velocity, an expected direction, an expected service profile, or an indicator for the UE to sense and report local surroundings; and sending, by the RAN node, a configuration message to the UE, the configuration message, so that the UE performs according to the at least one MDT configuration item and the optional NAS information and reports a MDT measurement result.

Abstract: Provided are an address allocation method and apparatus, a core network, a node, a network system and a medium. In at least one of the case of establishing a session, at least two uplink addresses are configured and send to an access network. The access network is a connectivity network formed by a coupling of at least two network element nodes. At least part of the at least two uplink addresses are used for being allocated among the network element nodes. The access network receives the at least two uplink addresses sent by the core network and allocates the at least two uplink addresses. The access network sends at least one downlink address to the core network and determines usage of the uplink addresses. The access network may determine a correspondence between the uplink address and the downlink address. The core network receives the downlink address.