Patents by Inventor Liang Chao
Liang Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11965833Abstract: A detection device includes a frame, a transport mechanism, detection mechanisms, and a grasping mechanism. The transport mechanism includes a feeding line, a first flow line, and a second flow line arranged in parallel on the frame. The detection mechanisms are arranged on the frame and located on two sides of the transport mechanism. The grasping mechanism is arranged on the frame and used to transport workpieces on the feeding line to the detection mechanisms, transport qualified workpieces to the first flow line, and transport unqualified workpieces to the second flow line.Type: GrantFiled: November 26, 2020Date of Patent: April 23, 2024Assignees: HONGFUJIN PRECISION ELECTRONICS (ZHENGZHOU) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Jing-Zhi Hou, Lin-Hui Cheng, Yan-Chao Ma, Jin-Cai Zhou, Zi-Long Ma, Neng-Neng Zhang, Yi Chen, Chen-Xi Tang, Meng Lu, Peng Zhou, Ling-Hui Zhang, Lu-Hui Fan, Shi-Gang Xu, Cheng-Yi Chao, Liang-Yi Lu
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Publication number: 20240105813Abstract: A semiconductor structure includes an interfacial layer disposed over a semiconductor channel region, a metal oxide layer disposed over the interfacial layer, a high-k gate dielectric layer disposed over the metal oxide layer, a metal halide layer disposed over the high-k gate dielectric layer, and a metal gate electrode disposed over the high-k gate dielectric layer. The metal oxide layer and the interfacial layer form a dipole moment. The metal oxide layer includes a first metal. The metal halide layer includes a second metal different from the first metal.Type: ApplicationFiled: November 28, 2023Publication date: March 28, 2024Inventors: Hsueh Wen Tsau, Ziwei Fang, Huang-Lin Chao, Kuo-Liang Sung
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Publication number: 20240090232Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Liang CHENG, Huang-Lin CHAO
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Publication number: 20240088227Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Liang CHENG, Chun-I WU, Huang-Lin CHAO
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Patent number: 11925033Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.Type: GrantFiled: March 30, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Liang Liu, Sheng-Chau Chen, Chung-Liang Cheng, Chia-Shiung Tsai, Yeong-Jyh Lin, Pinyen Lin, Huang-Lin Chao
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Patent number: 11007828Abstract: A valve stem structure disposed at a rim of a tire of a vehicle for connecting to an electronic tire pressure monitoring device in the tire is provided. The valve stem structure includes a tube, an air core, and a conducting wire. The tube has a first inlet, a first outlet communicating with an inner space of the tire, and a second outlet. The air core is switchably disposed at the first inlet, and a compressed air is injected into the tire via the first inlet and the first outlet by switching the air core. The conducting wire is disposed in the tube, and an end of the conducting wire extends out of the tube via the second outlet to be electrically connected to the electronic tire pressure monitoring device. A power source charges the electronic tire pressure monitoring device via the conducting wire.Type: GrantFiled: December 24, 2018Date of Patent: May 18, 2021Assignee: One Unique Inc.Inventors: Yuan-Lung Cheng, Kou-Liang Chao, Chieh-Yi Sung
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Patent number: 10964755Abstract: The present disclosure relates to an organic light emitting diode panel and a method for manufacturing the same, and a display device. The organic light emitting diode panel includes a light emitting function layer disposed on a substrate, wherein the light emitting function layer includes a first light emitting unit, a second light emitting unit, and a third light emitting unit, the first light emitting unit, the second light emitting unit, and the third light emitting unit emit light of three colors, a light exit side of at least one of the light emitting units is provided with a color filter layer that filters out blue light from light emitted by the at least one of the light emitting units.Type: GrantFiled: August 8, 2018Date of Patent: March 30, 2021Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.Inventors: Weilin Lai, Xiaoyun Liu, Liang Chao
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Publication number: 20190193491Abstract: A valve stem structure disposed at a rim of a tire of a vehicle for connecting to an electronic tire pressure monitoring device in the tire is provided. The valve stem structure includes a tube, an air core, and a conducting wire. The tube has a first inlet, a first outlet communicating with an inner space of the tire, and a second outlet. The air core is switchably disposed at the first inlet, and a compressed air is injected into the tire via the first inlet and the first outlet by switching the air core. The conducting wire is disposed in the tube, and an end of the conducting wire extends out of the tube via the second outlet to be electrically connected to the electronic tire pressure monitoring device. A power source charges the electronic tire pressure monitoring device via the conducting wire.Type: ApplicationFiled: December 24, 2018Publication date: June 27, 2019Applicant: One Unique Inc.Inventors: Yuan-Lung Cheng, Kou-Liang Chao, Chieh-Yi Sung
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Publication number: 20190157357Abstract: The present disclosure relates to an organic light emitting diode panel and a method for manufacturing the same, and a display device. The organic light emitting diode panel includes a light emitting function layer disposed on a substrate, wherein the light emitting function layer includes a first light emitting unit, a second light emitting unit, and a third light emitting unit, the first light emitting unit, the second light emitting unit, and the third light emitting unit emit light of three colors, a light exit side of at least one of the light emitting units is provided with a color filter layer that filters out blue light from light emitted by the at least one of the light emitting units.Type: ApplicationFiled: August 8, 2018Publication date: May 23, 2019Inventors: Weilin Lai, Xiaoyun Liu, Liang Chao
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Patent number: 9406745Abstract: A method of manufacturing super junction for semiconductor device is disclosed. The super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.Type: GrantFiled: July 23, 2015Date of Patent: August 2, 2016Assignee: PFC DEVICE HOLDINGS LIMITEDInventors: Paul Chung-Chen Chang, Kuo-Liang Chao, Mei-Ling Chen, Lung-Ching Kao
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Patent number: 9379180Abstract: A super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.Type: GrantFiled: December 12, 2013Date of Patent: June 28, 2016Assignee: PFC DEVICE HOLDINGS LIMITEDInventors: Paul Chung-Chen Chang, Kuo-Liang Chao, Mei-Ling Chen, Lung-Ching Kao
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Patent number: 9274626Abstract: A display apparatus includes a panel module, an assembly member, a glue layer, and a touch module. The assembly member is engaged with a sidewall of the panel module. The glue layer is disposed on the panel module and at least one portion of the glue layer is disposed on the assembly member. The touch module is disposed on the glue layer. The panel module and the assembly member are adhered to a first side of the glue layer. The touch module is adhered to a second side of the glue layer opposite to the first side.Type: GrantFiled: April 26, 2012Date of Patent: March 1, 2016Assignee: AU OPTRONICS CORPORATIONInventors: Shih-Ting Chen, Te-Hen Lo, Hao-Liang Chao
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Patent number: 9219170Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.Type: GrantFiled: October 29, 2014Date of Patent: December 22, 2015Assignee: PFC DEVICE HOLDINGS LTDInventors: Kou-Liang Chao, Mei-Ling Chen, Tse-Chuan Su, Hung-Hsin Kuo
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Publication number: 20150325643Abstract: A method of manufacturing super junction for semiconductor device is disclosed. The super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.Type: ApplicationFiled: July 23, 2015Publication date: November 12, 2015Inventors: Paul Chung-Chen CHANG, Kuo-Liang CHAO, Mei-Ling CHEN, Lung-Ching KAO
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Patent number: 9029235Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.Type: GrantFiled: May 26, 2014Date of Patent: May 12, 2015Assignee: PFC Device Corp.Inventors: Mei-Ling Chen, Hung-Hsin Kuo, Kuo-Liang Chao
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Publication number: 20150054115Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.Type: ApplicationFiled: October 29, 2014Publication date: February 26, 2015Inventors: Kou-Liang CHAO, Mei-Ling CHEN, Tse-Chuan SU, Hung-Hsin KUO
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Patent number: 8927401Abstract: A trench Schottky diode and its manufacturing method are provided. The trench Schottky diode includes a semiconductor substrate having therein a plurality of trenches, a gate oxide layer, a polysilicon structure, a guard ring and an electrode. At first, the trenches are formed in the semiconductor substrate by an etching step. Then, the gate oxide layer and the polysilicon structure are formed in the trenches and protrude above a surface of the semiconductor substrate. The guard ring is formed to cover a portion of the resultant structure. At last, the electrode is formed above the guard ring and the other portion not covered by the guard ring. The protruding gate oxide layer and the protruding polysilicon structure can avoid cracks occurring in the trench structure.Type: GrantFiled: January 7, 2013Date of Patent: January 6, 2015Assignee: PFC Device Corp.Inventors: Kou-Liang Chao, Hung-Hsin Kuo, Tse-Chuan Su, Mei-Ling Chen
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Patent number: 8921949Abstract: A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a central conductive layer, a silicon nitride layer, a metal diffusion layer, a channel region, and a metal sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. A silicon nitride layer is formed on the central conductive layer. A metal diffusion layer is formed within the guard ring and the central conductive layer. Afterwards, a metal sputtering layer is formed, and the mask layer is partially exposed.Type: GrantFiled: December 26, 2012Date of Patent: December 30, 2014Assignee: PFC Device Corp.Inventors: Kou-Liang Chao, Hung-Hsin Kuo, Tse-Chuan Su, Mei-Ling Chen
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Patent number: 8890279Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.Type: GrantFiled: November 15, 2013Date of Patent: November 18, 2014Assignee: PFC Device Corp.Inventors: Kou-Liang Chao, Mei-Ling Chen, Tse-Chuan Su, Hung-Hsin Kuo
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Publication number: 20140308799Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.Type: ApplicationFiled: May 26, 2014Publication date: October 16, 2014Applicant: PFC DEVICE CORP.Inventors: Mei-Ling Chen, Hung-Hsin Kuo, Kuo-Liang Chao