Patents by Inventor Liang Chao
Liang Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8927401Abstract: A trench Schottky diode and its manufacturing method are provided. The trench Schottky diode includes a semiconductor substrate having therein a plurality of trenches, a gate oxide layer, a polysilicon structure, a guard ring and an electrode. At first, the trenches are formed in the semiconductor substrate by an etching step. Then, the gate oxide layer and the polysilicon structure are formed in the trenches and protrude above a surface of the semiconductor substrate. The guard ring is formed to cover a portion of the resultant structure. At last, the electrode is formed above the guard ring and the other portion not covered by the guard ring. The protruding gate oxide layer and the protruding polysilicon structure can avoid cracks occurring in the trench structure.Type: GrantFiled: January 7, 2013Date of Patent: January 6, 2015Assignee: PFC Device Corp.Inventors: Kou-Liang Chao, Hung-Hsin Kuo, Tse-Chuan Su, Mei-Ling Chen
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Patent number: 8921949Abstract: A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a central conductive layer, a silicon nitride layer, a metal diffusion layer, a channel region, and a metal sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. A silicon nitride layer is formed on the central conductive layer. A metal diffusion layer is formed within the guard ring and the central conductive layer. Afterwards, a metal sputtering layer is formed, and the mask layer is partially exposed.Type: GrantFiled: December 26, 2012Date of Patent: December 30, 2014Assignee: PFC Device Corp.Inventors: Kou-Liang Chao, Hung-Hsin Kuo, Tse-Chuan Su, Mei-Ling Chen
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Patent number: 8890279Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.Type: GrantFiled: November 15, 2013Date of Patent: November 18, 2014Assignee: PFC Device Corp.Inventors: Kou-Liang Chao, Mei-Ling Chen, Tse-Chuan Su, Hung-Hsin Kuo
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Publication number: 20140308799Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.Type: ApplicationFiled: May 26, 2014Publication date: October 16, 2014Applicant: PFC DEVICE CORP.Inventors: Mei-Ling Chen, Hung-Hsin Kuo, Kuo-Liang Chao
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Patent number: 8853748Abstract: A method for manufacturing a rectifier with a vertical MOS structure is provided. A first trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first trench structure.Type: GrantFiled: January 8, 2014Date of Patent: October 7, 2014Assignee: PFC Device Corp.Inventors: Kuo-Liang Chao, Mei-Ling Chen, Hung-Hsin Kuo
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Patent number: 8809946Abstract: A wide trench termination structure for semiconductor device includes a wide trench structure defined on a semiconductor substrate and having a width larger than that of narrow trench structures on an active region of the semiconductor device, an oxide layer arranged on an inner face of the wide trench structure, at least one trench polysilicon layer arranged on the oxide layer and on inner sidewall of the wide trench structure, a metal layer arranged on the oxide layer not covered by the trench polysilicon layer and on the trench polysilicon layer, and a field oxide layer arranged on the semiconductor substrate and outside the wide trench structure.Type: GrantFiled: January 9, 2013Date of Patent: August 19, 2014Assignee: PFC Device Corp.Inventors: Hung-Hsin Kuo, Mei-Ling Chen, Kuo-Liang Chao
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Patent number: 8796808Abstract: A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.Type: GrantFiled: April 21, 2009Date of Patent: August 5, 2014Assignee: PFC Device Corp.Inventors: Kuo-Liang Chao, Hung-Hsin Kuo, Tse-Chuan Su
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Publication number: 20140167205Abstract: A super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.Type: ApplicationFiled: December 12, 2013Publication date: June 19, 2014Applicant: PFC DEVICE HOLDINGS LIMITEDInventors: Paul Chung-Chen CHANG, Kuo-Liang CHAO, Mei-Ling CHEN, Lung-Ching KAO
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Patent number: 8753963Abstract: A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.Type: GrantFiled: September 26, 2013Date of Patent: June 17, 2014Assignee: PFC Device Corp.Inventors: Lung-Ching Kao, Mei-Ling Chen, Kuo-Liang Chao, Hung-Hsin Kuo
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Patent number: 8735228Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.Type: GrantFiled: September 5, 2013Date of Patent: May 27, 2014Assignee: PFC Device Corp.Inventors: Mei-Ling Chen, Hung-Hsin Kuo, Kuo-Liang Chao
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Patent number: 8728878Abstract: A MOS P-N junction diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. The method for manufacturing such diode device includes several ion-implanting steps. After the gate structure is formed by isotropic etching using a patterned photo-resist layer as a mask, an ion-implanting step is performed using the patterned photo-resist layer as a mask to form a deeper doped sub-region. Then, another ion-implanting step is performed using the gate structure as a mask to form a shallower doped sub-region between the gate structure and the deeper doped sub-region. The formed MOS P-N junction diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.Type: GrantFiled: January 11, 2013Date of Patent: May 20, 2014Assignee: PFC Device Corp.Inventors: Kuo-Liang Chao, Hung-Hsin Kuo, Tse-Chuan Su
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Publication number: 20140131793Abstract: A method for manufacturing a rectifier with a vertical MOS structure is provided. A first trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first trench structure.Type: ApplicationFiled: January 8, 2014Publication date: May 15, 2014Applicant: PFC DEVICE CORP.Inventors: Kuo-Liang Chao, Mei-Ling Chen, Hung-Hsin Kuo
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Patent number: 8704298Abstract: A MOS diode includes a substrate with a mesa, a P-type semiconductor region with etched shallow trench surrounding the mesa, that cause an increasing metal contact area to reduce Vf value, a gate oxide layer arranged on the mesa, a polysilicon layer arranged on the gate oxide layer, and a shielding oxide layer arranged on the polysilicon layer. The termination structure includes a trench, an oxide layer arranged at least within the trench, at least one sidewall polysilicon layer arranged on the oxide layer within the trench. In the MOS diode, the shielding oxide layer is thicker than the gate oxide layer to prevent leaking current. The oxide layer and the sidewall polysilicon layer can enhance the reverse voltage tolerance of the MOS diode. A metal layer covers the polysilicon region, shielding oxide layer, semiconductor regions with etched shallow trench, termination region and some parts outside the termination region.Type: GrantFiled: March 14, 2013Date of Patent: April 22, 2014Assignee: PFC Device Corp.Inventors: Kuo-Liang Chao, Mei-Ling Chen, Lung-Ching Kao, Hung-Hsin Kuo
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Patent number: 8680590Abstract: A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.Type: GrantFiled: March 2, 2012Date of Patent: March 25, 2014Assignee: PFC Device Corp.Inventors: Lung-Ching Kao, Mei-Ling Chen, Kuo-Liang Chao, Hung-Hsin Kuo
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Publication number: 20140077328Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.Type: ApplicationFiled: November 15, 2013Publication date: March 20, 2014Applicant: PFC DEVICE CORP.Inventors: Kou-Liang CHAO, Mei-Ling CHEN, Tse-Chuan SU, Hung-Hsin KUO
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Patent number: 8664701Abstract: A method for manufacturing a rectifier with a vertical MOS structure is provided. A first trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first trench structure.Type: GrantFiled: April 13, 2012Date of Patent: March 4, 2014Assignee: PFC Device Corp.Inventors: Kuo-Liang Chao, Mei-Ling Chen, Hung-Hsin Kuo
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Publication number: 20140030882Abstract: A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.Type: ApplicationFiled: September 26, 2013Publication date: January 30, 2014Applicant: PFC DEVICE CORP.Inventors: Lung-Ching KAO, Mei-Ling CHEN, Kuo-Liang CHAO, Hung-Hsin KUO
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Publication number: 20140004681Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.Type: ApplicationFiled: September 5, 2013Publication date: January 2, 2014Applicant: PFC DEVICE CORP.Inventors: Mei-Ling Chen, Hung-Hsin Kuo, Kuo-Liang Chao
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Patent number: 8618626Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.Type: GrantFiled: October 12, 2010Date of Patent: December 31, 2013Assignee: PFC Device CorporationInventors: Kou-Liang Chao, Mei-Ling Chen, Tse-Chuan Su, Hung-Hsin Kuo
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Patent number: 8558315Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.Type: GrantFiled: July 26, 2011Date of Patent: October 15, 2013Assignee: PFC Device CorporationInventors: Mei-Ling Chen, Hung-Hsin Kuo, Kou-Liang Chao