Abstract: A circuit is provided for supplying a negative high voltage to an integrated circuit from a high positive voltage source V.sub.PP. The negative voltage is applied to a plurality of FLASH electrically erasable programmable read only memory (EPROM) cells. The circuit includes an oscillator coupled to a voltage converter which provides a periodic signal. The periodic signal is coupled to a charge pump including three P-channel type transistors to produce the negative voltage. The source and drain of the first transistor is coupled to the periodic signal. The second transistor's gate and drain is coupled to a reference ground potential with the source coupled to the first transistor's gate. Finally, the third transistor's drain and gate is coupled to the first transistor's gate and the third transistor's source outputs negative voltage to floating gates of the plurality of FLASH EPROM cells during an erase operation. Further, the negative voltage generated is relatively precise, so no regulation is required.

Abstract: For non-volatile memory devices, such as flash EPROM integrated circuits, which have memory cells and reference cells, and sense circuitry responsive to addressed memory cells and the reference cells, and in which a read potential is supplied to the gate of the selected memory cells and a reference potential is supplied to the gate of a reference memory cell during a read mode, the state of the programmable memory cells is verified by (1) supplying a first verify potential to the gate of an address programmable memory cell; and (2) supplying a second verify potential to the gate of the reference cell which is different from the first verify potential. Because cell current is a very strong function of the gate voltage, applying different gate voltages to the memory and reference cells is equivalent to adjusting the sense ratio.

Abstract: For non-volatile memory devices, such as flash EPROM integrated circuits, which have memory cells and reference cells, and sense circuitry responsive to addressed memory cells and the reference cells, and in which a read potential is supplied to the gate of the selected memory cells and a reference potential is supplied to the gate of a reference memory cell during a read mode, the state of the programmable memory cells is verified by (1) supplying a first verify potential to the gate of an address programmable memory cell; and (2) supplying a second verify potential to the gate of the reference cell which is different from the first verify potential. Because cell current is a very strong function of the gate voltage, applying different gate voltages to the memory and reference cells is equivalent to adjusting the sense ratio.

Abstract: A circuit is provided for supplying a negative high voltage to an integrated circuit from a high positive voltage source V.sub.PP. The negative voltage is applied to a plurality of FLASH electrically erasable programmable read only memory (EPROM) cells. The circuit includes an oscillator coupled to a voltage converter which provides a periodic signal. The periodic signal is coupled to a charge pump including three P-channel type transistors to produce the negative voltage. The source and drain of the first transistor is coupled to the periodic signal. The second transistor's gate and drain is coupled to a reference ground potential with the source coupled to the first transistor's gate. Finally, the third transistor's drain and gate is coupled to the first transistor's gate and the third transistor's source outputs negative voltage to floating gates of the plurality of FLASH EPROM cells during an erase operation. Further, the negative voltage generated is relatively precise, so no regulation is required.

Abstract: A hair-style simulation cassette has a back strip, a U-shaped frame fixed to the back strip, a panel fixed to the U-shaped frame, a film fixed to the panel, and a photograph carrier receivable in the U-shaped frame. The photograph carrier has a cavity for receiving a photograph. The panel has a viewing window through which the photograph is visible and an adjusting window through which the photograph is adjustable.

Abstract: A utility knife switchable between a non-rotatable mode for cutting a straight line and a rotatable mode for cutting a curved line includes a rod which engages to a blade at one end and the other end being rotatably positioned against a bearing device thereby providing the blade with a rotation axle for cutting a curve. A switching button device is installed above the limiting device for forcing the rod and the blade to work in a non-rotatable mode or a rotatable mode.