Patents by Inventor Liang LIAO

Liang LIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170229343
    Abstract: A method of forming a semiconductor structure includes; (i) forming an isolation structure in a semiconductor substrate, the isolation structure electrically isolating device regions of the semiconductor substrate; (ii) forming a gate structure extending from one of the device regions to the isolation structure; (iii) forming a resist protective oxide layer overlaying the gate structure and the isolation structure; and (iv) patterning the resist protective oxide layer to form a patterned resist protective oxide that covers at least a portion of the isolation structure and a portion of the gate structure on the isolation structure.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Liang LIAO, Chia-Yao LIANG, Jui-Long CHEN, Sheng-Yuan LIN, Yi-Lii HUANG, Kuo-Hsi LEE, Po-An CHEN
  • Patent number: 9727237
    Abstract: A method of managing a keypad of a handheld electronic device comprises promoting a user whether a size of the keypad needs adjustment when the handheld electronic device is in a single hand operating mode. If the answer is yes, the handheld electronic device then detects a movement of a finger of the user on a touch screen thereof. When a movement of the finger along a diagonal direction of the keypad away from the keypad is detected, the size of the keypad is increased. When a movement of the finger alone the diagonal direction of the keypad toward the keypad is detected, the size of the keypad is decreased. When the movement of the finger is stopped and a “Done” button is pressed, the adjustment of the size of the keypad is completed, and the size of the keypad after adjustment is stored in a storage module.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: August 8, 2017
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Cheng-Kuo Yang, Chien-Liang Liao, Yueh-Chi Wang
  • Publication number: 20170212564
    Abstract: A power supply device includes a housing, a plug assembly, and a sliding assembly. The plug assembly includes a power jack positioned on the housing and a power plug. The sliding assembly is slidably mounted on the housing. When the sliding assembly slides to a first position, the sliding assembly is configured to block the power jack for preventing the power plug being inserted to the power jack. When the sliding assembly slides to a second position, the sliding assembly is configured to move away from the power jack for allowing the power plug being received in the power jack.
    Type: Application
    Filed: March 15, 2016
    Publication date: July 27, 2017
    Inventor: FENG-LIANG LIAO
  • Patent number: 9708190
    Abstract: A method for producing a modified graphene includes the steps of intercalating or inserting a mixture of intercalating agents in a spacing between interlayers of carbon substrates or between carbon substrates, whereby the binding force between the interlayers of the carbon substrates or between the carbon substrates is weakened; and then exfoliating the pretreated carbon substrates to form the modified graphene. With the environmental friendly purpose, the method according to the present invention is useful for reducing the total amount of a strong acid. Therefore, the amount of the generated oxygen-containing functional groups attached on the modified graphene is modulated to avoid defects and maintain a yield over 80%.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: July 18, 2017
    Assignee: National Taiwan University of Science and Technology
    Inventors: Wei-Hung Chiang, Yen-Sheng Li, Jia-Liang Liao
  • Patent number: 9691867
    Abstract: The semiconductor device structures and methods for forming the same are provided. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: June 27, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Liang Liao, Chih-Hsiao Chen, Yi-Lii Huang, Yao-Yu Li
  • Patent number: 9633860
    Abstract: A semiconductor structure includes an isolation structure, a gate stack, a spacer and a patterned resist protective oxide. The isolation structure is formed in a semiconductor substrate, and electrically isolates device regions of the semiconductor substrate. The gate stack is located on the isolation structure. The spacer is formed along a sidewall of the gate stack on the isolation structure. The patterned resist protective oxide is located on the isolation structure and covers a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Liang Liao, Chia-Yao Liang, Jui-Long Chen, Sheng-Yuan Lin, Yi-Lii Huang, Kuo-Hsi Lee, Po-An Chen
  • Publication number: 20170011925
    Abstract: A semiconductor structure includes an isolation structure, a gate stack, a spacer and a patterned resist protective oxide. The isolation structure is formed in a semiconductor substrate, and electrically isolates device regions of the semiconductor substrate. The gate stack is located on the isolation structure. The spacer is formed along a sidewall of the gate stack on the isolation structure. The patterned resist protective oxide is located on the isolation structure and covers a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack.
    Type: Application
    Filed: July 9, 2015
    Publication date: January 12, 2017
    Inventors: Chen-Liang LIAO, Chia-Yao LIANG, Jui-Long CHEN, Sheng-Yuan LIN, Yi-Lii HUANG, Kuo-Hsi LEE, Po-An CHEN
  • Patent number: 9529956
    Abstract: The integrated circuit (IC) device includes a substrate, an isolation feature, a first gate structure, a second gate structure, a first contact feature and a first supplementary active region. The isolation feature is disposed in the substrate, and the isolation feature defines a boundary between a first active region and a second active region of the substrate. The first gate structure is disposed over the first active region. The second gate structure is disposed over the second active region. The first contact feature is disposed over the first active region, in which a portion of the first active region is disposed between the first gate structure and the isolation feature. The first supplementary active region is disposed adjacent to the portion of the first active region, in which a thickness of the first supplementary active region is substantially in a range from 5 nm to 10 nm.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: December 27, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Liang Liao, Cheng-Wei Cheng, Ming Lei, Yi-Lii Huang
  • Publication number: 20160359010
    Abstract: The semiconductor device structures and methods for forming the same are provided. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.
    Type: Application
    Filed: August 22, 2016
    Publication date: December 8, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO.,LTD.
    Inventors: Chen-Liang LIAO, Chih-Hsiao CHEN, Yi-lii HUANG, Yao-Yu LI
  • Publication number: 20160347619
    Abstract: Provided is a method for producing a modified graphene, comprising the steps of intercalating or inserting a mixture of intercalating agents in a spacing between interlayers of carbon substrates or between carbon substrates, whereby the binding force between the interlayers of the carbon substrates or between the carbon substrates is weaken; and then exfoliating the pretreated carbon substrates to form the modified graphene. Upon environmental friendly purpose, the method according to the present invention is useful for reducing the total amount of strong acid. Therefore, the amount of the generated oxygen-containing functional groups attached on the modified graphene is modulated to avoid defects and maintain a yield over 80%.
    Type: Application
    Filed: December 10, 2015
    Publication date: December 1, 2016
    Inventors: Wei-Hung Chiang, Yen-Sheng Li, Jia-Liang Liao
  • Patent number: 9425274
    Abstract: The semiconductor device structures and methods for forming the same are provided. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: August 23, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chen-Liang Liao, Chih-Hsiao Chen, Yi-Lii Huang, Yao-Yu Li
  • Patent number: 9407234
    Abstract: The present invention discloses a current balancing device and method capable of balancing an output current and an input current of a current loop. Said device comprises: a transmission circuit for outputting an output current and receiving an input current; at least one adjustable resistor set in the current loop for providing resistance according to at least one adjustment signal; and a current balancing circuit, coupled to the transmission circuit and the adjustable resistor, for determining whether the difference between the output and input currents satisfies a predetermined requirement in light of a predetermined duration and thereby generating the adjustment signal, wherein if the difference between the output and input currents fails to satisfy the predetermined requirement, the current balancing circuit will adjust the resistance of the adjustable resistor through the adjustment signal, so as to reduce the difference between the output and input currents.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: August 2, 2016
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shih-Wei Wang, Su-Liang Liao, Liang-Wei Huang, Sheng-Fu Chuang
  • Publication number: 20160203984
    Abstract: The semiconductor device structures and methods for forming the same are provided. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Liang LIAO, Chih-Hsiao CHEN, Yi-Lii HUANG, Yao-Yu LI
  • Publication number: 20160151900
    Abstract: A pneumatic nail gun operated in automatic actuation mode includes a gun body, a trigger valve, and a shuttle valve. The gun body defines therein a main chamber and is provided with a forward air conduit and a return air conduit. The forward air conduit provides a path for the pressurized air in the main chamber to force a valve stem of the shuttle valve to conduct a forward movement for a drive stroke. The return air conduit provides a path for the pressurized air in the cylinder to force the valve stem to conduct a return movement after the nail gun has completed the drive stroke. By depressing an actuating bar of the trigger valve a single time, the valve stem can be forced to conduct repeated forward and return movements, and thus the nail gun can conduct repeated drive strokes for stably striking a nail.
    Type: Application
    Filed: January 12, 2015
    Publication date: June 2, 2016
    Inventors: I-Tsung Wu, Hai-Lun Ma, Zhen-Liang Liao
  • Patent number: 9348374
    Abstract: A hard disk mounting mechanism can be used for assembling a hard disk into a housing defining an opening. The hard disk can be inserted into the housing via the opening. The hard disk mounting mechanism can include a mounting bracket and a slidable carrier. The mounting bracket can include a cover and a slidable carrier. The cover can be rotatably connected to the housing for covering the opening. The slidable carrier can be located in the housing adjacent to the opening, and has a first surface facing the opening. A first heat conductive pad can be arranged on the first surface of the slidable carrier. The hard disk can be assembled on the slidable carrier. The hard disk can contact with the first heat conductive pad from the opening when the cover is rotated to cover the opening.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: May 24, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Feng-Liang Liao, Tzu-Hsiu Hung
  • Patent number: 9349817
    Abstract: Embodiments of the disclosure provide semiconductor device structures and methods of forming the same. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: May 24, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chen-Liang Liao, Chih-Hsiao Chen, Yi-Lii Huang, Yao-Yu Li
  • Publication number: 20160116170
    Abstract: An ignition controlling device of a gas appliance includes a high-voltage provider, a controller, and a flame sensor. The gas appliance includes an ignition electrode and a burner, and the ignition electrode is beside burner. The high-voltage provider has an output terminal, and the output terminal is electrically connected to the ignition electrode to provide high-voltage pulses to the ignition electrode. The controller controls the high-voltage provider to provide the high-voltage pulses. The flame sensor is electrically connected to the output terminal of the high-voltage provider to detect a flame around the ignition electrode and the burner. After a flame is detected by the flame sensor, the controller controls the high-voltage provider to stop the high-voltage pulses.
    Type: Application
    Filed: October 22, 2014
    Publication date: April 28, 2016
    Applicant: GRAND MATE CO., LTD.
    Inventors: CHUNG-CHIN HUANG, CHIN-YING HUANG, HSIN-MING HUANG, HSING-HSIUNG HUANG, YEN-JEN YEH, KUAN-CHOU LIN, PEN-LIANG LIAO
  • Patent number: 9324864
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes an isolation structure positioned in the semiconductor substrate and adjacent to a first active region of the semiconductor substrate. The semiconductor device structure includes a gate stack disposed over the first active region. The semiconductor device structure includes a first contact structure disposed over the first active region and positioned between the isolation structure and the gate stack. The semiconductor device structure includes a dummy gate stack disposed over the isolation structure and adjacent to the gate stack. The dummy gate stack is not positioned over a portion of the isolation structure next to the first contact structure.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: April 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yao Liang, Chen-Liang Liao, Ming Lei, Chih-Hsiao Chen, Yi-Lii Huang
  • Patent number: 9316782
    Abstract: A coverless linear light source light guide with hooded bracket for holding a light emitting diode (LED) module to the light guide is disclosed. The hooded bracket is disposed around the light receiving end of the light guide and comprises a hood top, a hood back, two hood sides, and two hood grasps disposed on the hood sides. The hood back comprises the light receiving end of the light guide where light enters the light guide. The hood grasp comprises grasping elements that mate with grasping elements of the LED module to securely hold the LED module to the light guide. The hooded bracket ensures that the distance between the LED module and the light guide and the angle of the LED module and the light guide is constant which maintains optimal alignment and proximity in order to conserve received light intensity and maintain uniformity of emitted light.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: April 19, 2016
    Assignee: Pixon Technologies Corp.
    Inventors: Yen-Chieh Chen, Shih Che Chen, Chien Liang Liao
  • Publication number: 20160093736
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes an isolation structure positioned in the semiconductor substrate and adjacent to a first active region of the semiconductor substrate. The semiconductor device structure includes a gate stack disposed over the first active region. The semiconductor device structure includes a first contact structure disposed over the first active region and positioned between the isolation structure and the gate stack. The semiconductor device structure includes a dummy gate stack disposed over the isolation structure and adjacent to the gate stack. The dummy gate stack is not positioned over a portion of the isolation structure next to the first contact structure.
    Type: Application
    Filed: September 30, 2014
    Publication date: March 31, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yao LIANG, Chen-Liang LIAO, Ming LEI, Chih-Hsiao CHEN, Yi-Lii HUANG