Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

Abstract: A method for improving service continuity is provided. The method is implemented by a reduced capability (RedCap) user equipment (UE) and includes generating a not-allowed cell list of new radio (NR) standalone (SA) cells. The method includes avoiding performing a mobility decision on the NR SA cells recorded in the not-allowed cell list during a mobility procedure or a measurement reporting procedure.

Abstract: A semiconductor device includes a first wafer comprising a first portion of a seal ring structure within a body of the first wafer. The semiconductor device includes a second wafer comprising a second portion of the seal ring structure within a body of the second wafer. The second wafer is affixed to the first wafer such that the second portion of the seal ring structure is on the first portion of the seal ring structure. The semiconductor device includes a trench structure comprising a first trench in the first wafer and a second trench in the second wafer, where the first trench and the second trench are on a same side of the seal ring structure.

Abstract: A self-drilling expanding anchor bolt, including a drill bit for drilling, an anchor rod connected to the drill bit, and an expanding sleeve surrounding the anchor rod, the anchor rod having an expansion cone at a first end adjoining the drill bit, having a neck region behind and contiguous with the expansion cone, and having a threaded segment at a second end of the neck region remote from the drill bit, wherein the expansion cone expands the expanding sleeve in a radial direction when the expansion cone is pulled into the expanding sleeve; a transition part is provided between the drill bit and the expansion cone of the anchor rod, the maximum diameter of the transition part being smaller than the hole diameter of a drilled hole formed by the drill bit.

Abstract: The present disclosure relates to an integrated chip processing tool. The integrated chip processing tool includes a gas distribution ring configured to extend along a perimeter of a process chamber. The gas distribution ring includes a lower ring extending around the process chamber. The lower ring has a plurality of gas inlets arranged along a bottom surface of the lower ring and a plurality of gas conveyance channels arranged along an upper surface of the lower ring directly over the plurality of gas inlets. The gas distribution ring further includes an upper ring disposed on the upper surface of the lower ring and covering the plurality of gas conveyance channels. A plurality of gas outlets are arranged along opposing ends of the plurality of gas conveyance channels. A plurality of gas conveyance paths extending between the plurality of gas inlets and the plurality of gas outlets have approximately equal lengths.

Abstract: An electronic device includes a conductive layer, a first dielectric layer, and a second dielectric layer, in which the second dielectric layer is disposed on the first dielectric layer, the conductive layer is disposed between the first dielectric layer and the second dielectric layer, the first dielectric layer has a first transmittance for a light, the second dielectric layer has a second transmittance for the light, and the first transmittance is different from the second transmittance.

Abstract: A compound and the method for treating bacterial infections thereof are provided, wherein the compound is derived from AS101 and having a general formula (I) or a general formula (II), and wherein the method includes administering an effective amount of compound having the general formula (I) or a compound having the general formula (I) and its pharmaceutically acceptable salt thereof.

Abstract: A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.

Abstract: An electronic device including at least one light emitting chip, a circuit chip, and a base is provided. The base having a first surface, a second surface opposite to the first surface and at least one conductive via extending from the first surface to the second surface, the base is disposed between the at least one light emitting chip and the circuit chip, and the base is greater than one of the at least one light emitting chip in thickness. The circuit chip is electrically connected to the at least one light emitting chip through the at least one conductive via and configured to control the at least one light emitting chip.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Abstract: The present disclosure provides a semiconductor device with a plurality of semiconductor channel layers. The semiconductor channel layers include a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer. A strain in the second semiconductor layer is different from a strain in the first semiconductor layer. A gate is disposed over the plurality of semiconductor channel layers.

Abstract: A semiconductor device includes a first wafer comprising a first portion of a seal ring structure within a body of the first wafer. The semiconductor device includes a second wafer comprising a second portion of the seal ring structure within a body of the second wafer. The second wafer is affixed to the first wafer such that the second portion of the seal ring structure is on the first portion of the seal ring structure. The semiconductor device includes a trench structure comprising a first trench in the first wafer and a second trench in the second wafer, where the first trench and the second trench are on a same side of the seal ring structure.

Abstract: In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a conductive structure on a substrate. A removal process is performed to remove a portion of the dielectric layer to expose a portion of the conductive structure. The substrate is transported into a cleaning chamber having a wafer chuck below a bell jar structure. A cleaning process is performed to clean the exposed portion of the conductive structure by turning on a noble gas source to introduce a noble gas within the cleaning chamber, turning on an oxygen gas source to introduce oxygen within the cleaning chamber, applying a first bias to a plasma coil to form a plasma gas, and applying a second bias to the wafer chuck. The substrate is removed from the cleaning chamber. A conductive layer is formed over the dielectric layer and coupled to the conductive structure.

Abstract: The present invention relates to novel fungicidal compositions, to their use in agriculture or horticulture for controlling diseases caused by phytopathogens, especially phytopathogenic fungi, and to methods of controlling diseases on useful plants.

Abstract: The present disclosure provides novel crystalline forms of a compound that acts as a CDK9 modulator, processes for preparing the novel crystalline forms of a compound that acts as a CDK9 modulator, and uses thereof.

Abstract: Representative embodiments disclose machine learning classifiers used in scenarios such as speech recognition, image captioning, machine translation, or other sequence-to-sequence embodiments. The machine learning classifiers have a plurality of time layers, each layer having a time processing block and a depth processing block. The time processing block is a recurrent neural network such as a Long Short Term Memory (LSTM) network. The depth processing blocks can be an LSTM network, a gated Deep Neural Network (DNN) or a maxout DNN. The depth processing blocks account for the hidden states of each time layer and uses summarized layer information for final input signal feature classification. An attention layer can also be used between the top depth processing block and the output layer.

Abstract: The present disclosure relates to a class of JAK inhibitor compounds and uses thereof. Specifically, the present disclosure discloses a compound represented by formula (G), isotopically labeled compound thereof, or optical isomer thereof, geometric isomer thereof, a tautomer thereof or a mixture of various isomers, or a pharmaceutically acceptable salt thereof, or a prodrug thereof, or a metabolite thereof. The present disclosure also relates to the application of the compounds in medicine.

Abstract: A setting device for a self-drilling anchor bolt of the present invention includes: a drive shaft, one end thereof having a shank for connecting to an impact tool, and another end being a setting part for pushing the self-drilling anchor bolt axially; a coupling, partially surrounding the drive shaft along an axis, and being supported on the drive shaft in such a way as to be incapable of relative rotation while being axially moveable at least locally; and a releasable locking component, disposed between the drive shaft and the coupling; in a locked position, the locking component is coupled to an extremity of an anchor rod such that the anchor rod is fed axially with rotational striking into a receiving material, and in a released position, the drive shaft strikes a sleeve to advance axially along the anchor rod and expand at an expansion part.

Abstract: A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.