Patents by Inventor Liang Lu

Liang Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055452
    Abstract: A semiconductor image sensing structure includes a substrate, an isolation structure, an anti-reflection structure, at least one optical element and a transistor. The substrate has at least one photodiode region. The isolation structure is disposed in the substrate and surrounds the photodiode region. The anti-reflection structure covers the photodiode region. The optical element is disposed over the anti-reflection structure and corresponds to the photodiode region. The transistor is disposed under the photodiode region.
    Type: Application
    Filed: August 9, 2022
    Publication date: February 15, 2024
    Inventors: MING-HSIEN YANG, CHUN-LIANG LU, CHUN-HAO CHOU, KUO-CHENG LEE
  • Publication number: 20240018158
    Abstract: The present disclosure provides bifunctional compounds comprising a target protein binding moiety and a E3 ubiquitin ligase binding moiety, and associated methods of use.
    Type: Application
    Filed: May 15, 2023
    Publication date: January 18, 2024
    Inventors: Hong Lin, Philip Pitis, Liang Lu, Andrew Paul Combs
  • Publication number: 20240006425
    Abstract: An image sensor includes a substrate having first and second surfaces opposite to each other, an image pixel area, and a black level calibration (BLC) area adjacent to the image pixel area. The BLC area includes a dark current sensing circuit including photo diodes disposed in the substrate, a first seal ring disposed over the second surface and surrounding the image pixel area in plan view, a second seal ring disposed over the second surface and surrounding the image pixel area in plan view such that the dark current sensing circuit is disposed between the first and second seal rings, an opaque cover disposed over the first surface and covering the dark current sensing circuit, the first and second seal rings, and one or more first trench isolation structures extending from the first surface to an inside the substrate and disposed between the first seal ring and the opaque cover.
    Type: Application
    Filed: March 24, 2023
    Publication date: January 4, 2024
    Inventors: Ming-Hsien YANG, Chun-Hao CHOU, Kuo-Cheng LEE, Chun-Wei CHIA, Chun-Liang LU, Wei-Chih WENG, Cheng-Hao CHIU
  • Publication number: 20230420222
    Abstract: The present disclosure relates to an integrated chip processing tool. The integrated chip processing tool includes a gas distribution ring configured to extend along a perimeter of a process chamber. The gas distribution ring includes a lower ring extending around the process chamber. The lower ring has a plurality of gas inlets arranged along a bottom surface of the lower ring and a plurality of gas conveyance channels arranged along an upper surface of the lower ring directly over the plurality of gas inlets. The gas distribution ring further includes an upper ring disposed on the upper surface of the lower ring and covering the plurality of gas conveyance channels. A plurality of gas outlets are arranged along opposing ends of the plurality of gas conveyance channels. A plurality of gas conveyance paths extending between the plurality of gas inlets and the plurality of gas outlets have approximately equal lengths.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 28, 2023
    Inventors: Po-Hsiang Wang, Min-Chang Ching, Kuo Liang Lu, Bo-Han Chu
  • Patent number: 11855093
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
  • Publication number: 20230410730
    Abstract: An electronic device including a plurality of light-emitting units, a driving circuit, and a controlling circuit is provided. The driving circuit is configured to drive at least one of the light-emitting units. The controlling circuit is configured to control the driving circuit. The plurality of light-emitting units, the driving circuit, and the controlling circuit are respectively disposed on different substrate.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Applicant: Innolux Corporation
    Inventors: Ker-Yih Kao, Ming Chun Tseng, Liang-Lu Chen, Li-Wei Mao, Shun-Yuan Hu
  • Patent number: 11840534
    Abstract: The present invention relates to tricyclic compounds, and pharmaceutical compositions of the same, that are inhibitors of one or more FGFR enzymes and are useful in the treatment of FGFR-associated diseases such as cancer.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: December 12, 2023
    Assignees: Incyte Corporation, Incyte Holdings Corporation
    Inventors: Liangxing Wu, Colin Zhang, Chunhong He, Liang Lu, Wenqing Yao
  • Patent number: 11836231
    Abstract: A smart terminal unlocking method and device employing an Android system, and a smart terminal are provided. The method includes that: a smart terminal receives a system unlocking operation performed by a user to acquire unlocking information; determines, according to the unlocking information, whether a system of the smart terminal is allowed to be unlocked; determines whether a lock screen program of a third-party application is running when the system is allowed to be unlocked; shuts the lock screen program of the third-party application when the lock screen program of the third-party application is running, and unlocks the system to enter a system interface; and directly unlocks the system to enter the system interface when the lock screen program of the third-party application is not running.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 5, 2023
    Assignee: GREE ELECTRIC APPLIANCES, INC. OF ZHUHAI
    Inventor: Liang Lu
  • Publication number: 20230387245
    Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Liang LU, Chang-Yin CHEN, Chih-Han LIN, Chia-Yang LIAO
  • Publication number: 20230378266
    Abstract: A device comprise a first semiconductor channel layer over a substrate, a second semiconductor channel layer over the first semiconductor channel layer, and source/drain epitaxial structures on opposite sides of the first semiconductor channel layer and opposite sides of the second semiconductor channel layer. A compressive strain in the second semiconductor channel layer is greater than a compressive strain in the first semiconductor channel layer. The source/drain epitaxial structures each comprise a first region interfacing the first semiconductor channel layer and a second region interfacing the second semiconductor channel layer, and the first region has a composition different from a composition of the second region.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-En TSAI, Chia-Che CHUNG, Chee-Wee LIU, Fang-Liang LU, Yu-Shiang HUANG, Hung-Yu YEH, Chien-Te TU, Yi-Chun LIU
  • Publication number: 20230374025
    Abstract: The present disclosure relates to FGFR inhibitor compounds and its use. Specifically, the present disclosure discloses a compound represented by formula (I), isotopically labeled compound thereof, or optical isomer thereof, geometric isomer thereof, a tautomer thereof or a mixture of various isomers, or a pharmaceutically acceptable salt thereof, or a prodrug thereof, or a metabolite thereof. The present disclosure also relates to use of the above compound in medicine.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 23, 2023
    Inventors: Liang Lu, Saisai Zhao, Hai Huang, Longzheng Zhang, Jixuan Zhang, Jiaxin Chen, Shancun Ling
  • Publication number: 20230369487
    Abstract: A semiconductor device includes a first layer that includes a first semiconductor material disposed on a semiconductor substrate, and a second layer of a second semiconductor material disposed on the first layer. The semiconductor substrate includes Si. The first semiconductor material and the second semiconductor material are different. The second semiconductor material is formed of an alloy including a first element and Sn. A surface region of an end portion of the second layer at both ends of the second layer has a higher concentration of Sn than an internal region of the end portion of the second layer. The surface region surrounds the internal region.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Fang-Liang LU, I-Hsieh Wong, Shih-Ya Lin, CheeWee Liu, Samuel C. Pan
  • Publication number: 20230365576
    Abstract: The disclosure is directed to compounds of Formula I Pharmaceutical compositions comprising compounds of Formula I, as well as methods of their use and preparation, are also described.
    Type: Application
    Filed: May 9, 2023
    Publication date: November 16, 2023
    Inventors: John A. Rose, Corey Howard Basch, Song Mei, Klare Lazor Bersh, Danielle Roth, Katarina Rohlfing, Xiaowei Wu, Artem Shvartsbart, Andrew Paul Combs, Liang Lu
  • Publication number: 20230361140
    Abstract: Provided is an image sensor and a method of forming the same. The image sensor includes a first substrate having a first surface and a second surface opposite to each other; a plurality of photodetectors, disposed in the first substrate; and a plurality of color filters, disposed on the second surface of the first substrate and respectively corresponding to the plurality of photodetectors. The plurality of color filters are composed of a plurality of PIN diodes, and the plurality of PIN diodes are configured to absorb light of different wavelength ranges by applying different bias voltages.
    Type: Application
    Filed: May 6, 2022
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Liang Lu, Ming-Hsien Yang, Chun-Hao Chou, Kuo-Cheng Lee
  • Patent number: 11798639
    Abstract: A memory device and an operation method thereof are disclosed. The memory device includes a P-well region, a common source line, a ground selection line, at least one dummy ground selection line, a plurality of word lines, at least one dummy string selection line, a string selection line, at least one bit line and at least one memory string. The gates of a plurality of memory cells of the memory string are connected to the word lines. The operation method includes the following steps. Performing a read operation and applying a read voltage on the selected word line. Applying a pass voltage on other unselected word lines and the ground selection lines, etc. Before ending of the read operation, firstly decreasing voltages of the string selection line and the dummy string selection line in advance, then increasing voltage of the bit line.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: October 24, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Guan-Wei Wu, Yao-Wen Chang, Chun-Liang Lu, I-Chen Yang
  • Patent number: 11791410
    Abstract: A semiconductor device includes a first layer that includes a first semiconductor material disposed on a semiconductor substrate, and a second layer of a second semiconductor material disposed on the first layer. The semiconductor substrate includes Si. The first semiconductor material and the second semiconductor material are different. The second semiconductor material is formed of an alloy including a first element and Sn. A surface region of an end portion of the second layer at both ends of the second layer has a higher concentration of Sn than an internal region of the end portion of the second layer. The surface region surrounds the internal region.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fang-Liang Lu, I-Hsieh Wong, Shih-Ya Lin, CheeWee Liu, Samuel C. Pan
  • Patent number: 11790839
    Abstract: An electronic device including a plurality of light-emitting units, a driving circuit, and a controlling circuit is provided. The driving circuit is configured to drive at least one of the light-emitting units. The controlling circuit is configured to control the driving circuit. The plurality of light-emitting units, the driving circuit, and the controlling circuit are respectively disposed on different substrates.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: October 17, 2023
    Assignee: Innolux Corporation
    Inventors: Ker-Yih Kao, Ming Chun Tseng, Liang-Lu Chen, Li-Wei Mao, Shun-Yuan Hu
  • Patent number: 11791835
    Abstract: The present invention provides a computer-implemented method, computer system and computer program product for data compression. According to the computer-implemented method, one or more data blocks on a data source to be replicated to a data target may be detected. Then, compression performance of a first compression dictionary may be evaluated. The first compression dictionary may be previously used to compress existing data on the data target. If the compression performance is lower than a preset performance threshold, a second compression dictionary may be generated based on the existing data on the data target. The data target may be updated based on the existing data and the one or more data blocks using the second compression dictionary.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: October 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Xiao Wei Zhang, Hao Zhang, Meng Guo, Liang Lu, Jing F Fan, Jing Huang, Deng Ke Zhao
  • Publication number: 20230325581
    Abstract: A font switching method and an electronic device are provided. A target font consistent with a font currently used by an operating system is found through pixel matching of a dot matrix, and the target font is applied to a third-party application, so that the third-party application can accurately vary with a font change of the operating system. This avoids a problem that the font used by the third-party application software is inconsistent with the font used by the operating system.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 12, 2023
    Inventors: Liang Lu, Yaoming Liu, Lin Peng
  • Publication number: 20230326815
    Abstract: A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.
    Type: Application
    Filed: June 15, 2023
    Publication date: October 12, 2023
    Inventors: Chun-Liang LU, Chun-Wei CHIA, Chun-Hao CHOU, Kuo-Cheng LEE