Patents by Inventor Liang Lu

Liang Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11658207
    Abstract: The disclosure provides a capacitor and an electronic device. The capacitor is disposed on a substrate with a protrusion. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode has a first voltage. The second electrode has a second voltage different from the first voltage. The second electrode is closer to the substrate than the first electrode. The insulating layer is disposed between the first electrode and the second electrode. The protrusion penetrates the second electrode and extends into the insulating layer. The electronic device includes the capacitor. The capacitor and the electronic device of the embodiments in the disclosure have a better yield.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: May 23, 2023
    Assignee: Innolux Corporation
    Inventors: Ker-Yih Kao, Ming Chun Tseng, Liang-Lu Chen
  • Patent number: 11657799
    Abstract: Techniques performed by a data processing system for training a Recurrent Neural Network Transducer (RNN-T) herein include encoder pretraining by training a neural network-based token classification model using first token-aligned training data representing a plurality of utterances, where each utterance is associated with a plurality of frames of audio data and tokens representing each utterance are aligned with frame boundaries of the plurality of audio frames; obtaining first cross-entropy (CE) criterion from the token classification model, wherein the CE criterion represent a divergence between expected outputs and reference outputs of the model; pretraining an encoder of an RNN-T based on the first CE criterion; and training the RNN-T with second training data after pretraining the encoder of the RNN-T. These techniques also include whole-network pre-training of the RNN-T.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: May 23, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Rui Zhao, Jinyu Li, Liang Lu, Yifan Gong, Hu Hu
  • Publication number: 20230154467
    Abstract: A computing system including one or more processors configured to receive an audio input. The one or more processors may generate a text transcription of the audio input at a sequence-to-sequence speech recognition model, which may assign a respective plurality of external-model text tokens to a plurality of frames included in the audio input. Each external-model text token may have an external-model alignment within the audio input. Based on the audio input, the one or more processors may generate a plurality of hidden states. Based on the plurality of hidden states, the one or more processors may generate a plurality of output text tokens. Each output text token may have a corresponding output alignment within the audio input. For each output text token, a latency between the output alignment and the external-model alignment may be below a predetermined latency threshold. The one or more processors may output the text transcription.
    Type: Application
    Filed: January 20, 2023
    Publication date: May 18, 2023
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Yashesh GAUR, Jinyu LI, Liang LU, Hirofumi INAGUMA, Yifan GONG
  • Publication number: 20230144528
    Abstract: The disclosure is directed to, in part, to CDK inhibitors, pharmaceutical compositions comprising the same, as well as methods of their use and preparation.
    Type: Application
    Filed: September 30, 2022
    Publication date: May 11, 2023
    Inventors: Liang Lu, Rupa Shetty, Andrew Paul Combs, Chaofeng Dai, Raul Andrew Leal, Klare Lazor Bersch
  • Publication number: 20230139432
    Abstract: The present disclosure relates to a method for supplying blockchain computing power and a system thereof. The method comprises the steps of: receiving a computing power purchase request sent by a user-side terminal; generating purchase result data according to the computing power purchase request; scheduling a first blockchain server to provide users with computing service according to the purchase result data; when the first blockchain server stops serving, starting timing to obtain the target duration; judging whether the first blockchain server restarts the service when the target duration is less than the preset duration threshold, and obtaining a preset result; when the preset result is YES, improving the computing power of the first blockchain server correspondingly, so that the total service duration of the user and the actually obtained total computing power remain unchanged; when the preset result is NO, scheduling a second blockchain server to provide users with computing service.
    Type: Application
    Filed: January 18, 2022
    Publication date: May 4, 2023
    Inventor: Liang LU
  • Publication number: 20230132657
    Abstract: The present invention relates to a blockchain server computing capability allocation method and system.
    Type: Application
    Filed: February 22, 2022
    Publication date: May 4, 2023
    Inventor: Liang LU
  • Patent number: 11629148
    Abstract: The present disclosure relates to substituted pyrrollo[3,4-D]imidazoles as JAK inhibitor compounds and uses thereof. Specifically, the present disclosure discloses a compound represented by formula (I), optical isomer thereof, geometric isomer thereof, a tautomer thereof or a mixture of various isomers, or a pharmaceutically acceptable salt thereof, or a prodrug thereof, or a metabolite thereof. The present disclosure also relates to the application of the compounds in the treatment of JAK-related diseases or disorders.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: April 18, 2023
    Assignee: HENAN MEDINNO PHARMACEUTICAL TECHNOLOGY CO., LTD.
    Inventors: Liang Lu, Hai Huang, Longzheng Zhang, Saisai Zhao, Jixuan Zhang
  • Patent number: 11631399
    Abstract: According to some embodiments, a machine learning model may include an input layer to receive an input signal as a series of frames representing handwriting data, speech data, audio data, and/or textual data. A plurality of time layers may be provided, and each time layer may comprise a uni-directional recurrent neural network processing block. A depth processing block may scan hidden states of the recurrent neural network processing block of each time layer, and the depth processing block may be associated with a first frame and receive context frame information of a sequence of one or more future frames relative to the first frame. An output layer may output a final classification as a classified posterior vector of the input signal. For example, the depth processing block may receive the context from information from an output of a time layer processing block or another depth processing block of the future frame.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: April 18, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jinyu Li, Vadim Mazalov, Changliang Liu, Liang Lu, Yifan Gong
  • Patent number: 11626084
    Abstract: An electronic device coupled to a display includes a graphics card and a processor. The graphics card reads the extended display identification data from the display. The processor determines, according to the extended display identification data, that the display is able to display a default resolution at a first refresh rate at most, and determines, according to the extended display identification data, whether the display device is able to display the default resolution at a second refresh rate that exceeds the first refresh rate. When it is determined that the display is able to display the default resolution at the second refresh rate, the processor adds the second refresh rate into the extended display identification data.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: April 11, 2023
    Assignee: ACER INCORPORATED
    Inventors: Jun-Liang Lu, Hsin-Yu Chen
  • Publication number: 20230083376
    Abstract: The present disclosure provides bifunctional compounds comprising a target protein binding moiety and a E3 ubiquitin ligase binding moiety, and associated methods of use.
    Type: Application
    Filed: November 8, 2021
    Publication date: March 16, 2023
    Inventors: Liang Lu, Andrew Paul Combs, Corey Howard Basch, Rupa Shetty, Chaofeng Dai, Klare Lazor Bersch, John A. Rose, Danielle Julie Beam, Song Mei
  • Publication number: 20230085198
    Abstract: A method for manufacturing a multi-layered structure on a supporting entity is provided. The method includes forming a first layer and a first test mark on the supporting entity, wherein the first test mark has a first predetermined length. The first projected length of the first test mark is measured in a top view. The first warpage degree of the first test mark is calculated according to the first predetermined length and the first projected length.
    Type: Application
    Filed: November 18, 2021
    Publication date: March 16, 2023
    Inventors: Liang-Lu CHEN, Kuang-Ming FAN, Chia-Lin YANG
  • Publication number: 20230073714
    Abstract: An electronic device including a plurality of light-emitting units, a driving circuit, and a controlling circuit is provided. The driving circuit is configured to drive at least one of the light-emitting units. The controlling circuit is configured to control the driving circuit. The plurality of light-emitting units, the driving circuit, and the controlling circuit are respectively disposed on different substrates.
    Type: Application
    Filed: November 10, 2022
    Publication date: March 9, 2023
    Applicant: Innolux Corporation
    Inventors: Ker-Yih Kao, Ming Chun Tseng, Liang-Lu Chen, Li-Wei Mao, Shun-Yuan Hu
  • Publication number: 20230074496
    Abstract: The present disclosure is directed to semiconductor structures with source/drain epitaxial stacks having a low-melting point top layer and a high-melting point bottom layer. For example, a semiconductor structure includes a gate structure disposed on a fin and a recess formed in a portion of the fin not covered by the gate structure. Further, the semiconductor structure includes a source/drain epitaxial stack disposed in the recess, where the source/drain epitaxial stack has bottom layer and a top layer with a higher activated dopant concentration than the bottom layer.
    Type: Application
    Filed: November 14, 2022
    Publication date: March 9, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Hsien TU, Chee-Wee LIU, Fang-Liang LU
  • Publication number: 20230062974
    Abstract: In some embodiments, the present disclosure relates to a process tool that includes a chamber housing defining a processing chamber. Within the processing chamber is a wafer chuck configured to hold a substrate. Further, a bell jar structure is arranged over the wafer chuck such that an opening of the bell jar structure faces the wafer chuck. A plasma coil is arranged over the bell jar structure. An oxygen source coupled to the processing chamber and configured to input oxygen gas into the processing chamber.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Yen-Liang Lin, Chia-Wen Zhong, Yao-Wen Chang, Min-Chang Ching, Kuo Liang Lu, Cheng-Yuan Tsai, Ru-Liang Lee
  • Publication number: 20230049123
    Abstract: An electronic device is disclosed and includes a conductive layer, a first dielectric layer, and a second dielectric layer, in which the second dielectric layer is disposed on the first dielectric layer, the conductive layer is disposed between the first dielectric layer and the second dielectric layer, the first dielectric layer has a first transmittance for a light, the second dielectric layer has a second transmittance for the light, and the first transmittance is different from the second transmittance.
    Type: Application
    Filed: May 4, 2022
    Publication date: February 16, 2023
    Applicant: InnoLux Corporation
    Inventors: Kuang-Ming FAN, Chia-Lin YANG, Liang-Lu CHEN
  • Publication number: 20230043187
    Abstract: The present disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a connecting element. The connecting element includes a first conductive line segment, a second conductive line segment, and a first connecting line segment. The first conductive line segment is electrically connected to the second conductive line segment through the first connecting line segment. In a vertical projection direction, the first connecting line segment has a first height, the first conductive line segment has a second height, and the first height is different from the second height.
    Type: Application
    Filed: November 16, 2021
    Publication date: February 9, 2023
    Applicant: InnoLux Corporation
    Inventors: Cheng-Chi WANG, Kuang-Ming FAN, Liang-Lu CHEN, Chia-Lin YANG
  • Patent number: 11573983
    Abstract: Provided is a method, computer program product, and system for classifying a set of data items based on format organizations. A processor may determine at least one format organization of a set of data items. The format organization of a data item indicates a symbol type of at least one continuous symbol in the data item and a number of the at least one continuous symbol. The processor may determine at least one candidate data class for the set of data items from a plurality of predetermined data classes based on the at least one format organization. The processor may classify the set of data items into at least one target data class selected from the at least one candidate data class. In this way, the set of data items can be efficiently classified.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: February 7, 2023
    Assignee: International Business Machines Corporation
    Inventors: Liang Lu, Yue Wang, Sun Chun Hua, Jian Ling Shi, Yi Yang Ren, Chun Leng
  • Patent number: 11562745
    Abstract: A computing system including one or more processors configured to receive an audio input. The one or more processors may generate a text transcription of the audio input at a sequence-to-sequence speech recognition model, which may assign a respective plurality of external-model text tokens to a plurality of frames included in the audio input. Each external-model text token may have an external-model alignment within the audio input. Based on the audio input, the one or more processors may generate a plurality of hidden states. Based on the plurality of hidden states, the one or more processors may generate a plurality of output text tokens. Each output text token may have a corresponding output alignment within the audio input. For each output text token, a latency between the output alignment and the external-model alignment may be below a predetermined latency threshold. The one or more processors may output the text transcription.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: January 24, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yashesh Gaur, Jinyu Li, Liang Lu, Hirofumi Inaguma, Yifan Gong
  • Publication number: 20230011293
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.
    Type: Application
    Filed: July 9, 2021
    Publication date: January 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
  • Patent number: 11551992
    Abstract: A device includes plural semiconductor fins, a gate structure, an interlayer dielectric (ILD) layer, and an isolation dielectric. The gate structure is across the semiconductor fins. The ILD surrounds the gate structure. The isolation dielectric is at least between the semiconductor fins and has a thermal conductivity greater than a thermal conductivity of the ILD layer.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: January 10, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jhih-Yang Yan, Fang-Liang Lu, Chee-Wee Liu