Abstract: The invention provides a layout pattern of static random-access memory (SRAM), which comprises a substrate, wherein a plurality of diffusion regions and a plurality of gate structures are located on the substrate to form a plurality of transistors, wherein the plurality of gate structures comprise a first gate structure, which has a stepped shape when viewed from a top view, and the first gate structure spans a first diffusion region and a second diffusion region to form a first access transistor (PG1), wherein the first diffusion region is adjacent to and in direct contact with the second diffusion region.

Abstract: Embodiments of the present disclosure relate to the field of video coding and decoding, and provide a picture decoding method, a picture coding method, and corresponding apparatuses. According to an example of the picture decoding method, a quantization parameter (QP) value of at least one pixel point is determined for any at least one pixel point indicating one pixel point or a plurality of parallel dequantized pixel points in the current coding block, the QP values of at least two pixel points among pixel points in the current coding block being different. The at least one pixel point is then dequantized according to the QP value of the at least one pixel point. The QP value of each pixel point is determined for the coding block; therefore, each pixel point can be dequantized according to the QP value of each pixel point.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a first transistor and a second transistor formed over a first side of a substrate, forming a first multi-layer interconnect (MLI) structure over the first side of the substrate, wherein the first MLI structure comprising a first plurality of metal lines and a first plurality of vias, after the forming of the first MLI structure, forming a source/drain contact directly under a source/drain feature of the first transistor, and forming a second MLI structure under the source/drain contact and under a second side of the substrate, the second side being opposite the first side, wherein the MLI structure comprises a second plurality of metal lines and a second via, a thickness of the second via is greater than a thickness of one of the first plurality of vias.

Abstract: A medical apparatus comprises: an operating console, a limiting mechanism, and a manual release mechanism. The limiting mechanism releases the limitation on movement of the operating console in a case where a pressing force is applied to the manual release mechanism. The manual release mechanism comprises: a handle, a conversion portion, and a base portion. The handle is provided with a first guide portion. The base portion is provided with a second guide portion that cooperates with the first guide portion. The handle moves linearly in a direction substantially perpendicular to the base portion under guidance of the first guide portion and the second guide portion in a case where the pressing force is applied to the handle. Thus, a smooth linear motion of the handle can be ensured to provide a good feeling of operation, helping to improve the user experience.

Abstract: A method includes forming first integrated circuits on a front side of a semiconductor substrate of a first device die, forming a trench capacitor extending from a backside of the semiconductor substrate into the semiconductor substrate, and forming a first through-via and a second through-via penetrating through the semiconductor substrate. The trench capacitor is electrically coupled between the first through-via and the second through-via. A second device die is bonded to the first die. The second device die includes second integrated circuits, and power nodes of the second integrated circuits are electrically coupled to the first through-via and the second through-via.

Abstract: Semiconductor devices having dummy regions with dummy fill structures that vary in lateral dimensions and methods for forming the semiconductor devices are provided herein. The semiconductor devices may include a through silicon via extending through a substrate of the semiconductor device, an active device in or on the substrate, and a dummy region of the substrate separating the through silicon via and the active device, the dummy region including dummy fill structures, wherein the dummy fill structures have lateral dimensions measured in a first direction from the through silicon via to the active device, wherein the lateral dimensions of the dummy fill structures varying in the first direction.

Abstract: An embodiment is a device including a first die and a substrate including a first surface and a second surface opposite the first surface. The device also includes an active device on the first surface of the substrate. The device also includes a first interconnect structure on the first surface of the substrate. The device also includes a through substrate via extending through the first interconnect structure and the substrate to the second surface of the substrate, the through substrate via being electrically coupled to metallization patterns in the first interconnect structure. The device also includes one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the through substrate via.

Abstract: A method includes forming first nanostructures over a first region of a substrate; forming second nanostructures over a second region of the substrate; forming first gate structures around the first nanostructures; replacing the second nanostructures with isolation regions; and forming a seal ring over the substrate, wherein the seal ring is between the first region and the second region.

Abstract: A layout pattern of static random-access memory (SRAM) includes a substrate, a plurality of diffusion regions and a plurality of gate structures are located on the substrate, each diffusion region includes a first diffusion region, a second diffusion region, a third diffusion region, a fourth diffusion region, a fifth diffusion region, a sixth diffusion region, a seventh diffusion region and an eighth diffusion region, and each gate structure spans the plurality of diffusion regions. The plurality of gate structures include a first gate structure, the first gate structure includes a first L-shaped portion, which spans the first diffusion region and the fifth diffusion region and forms a first pull-down transistor (PD1), the first diffusion region is adjacent to and in direct contact with the fifth diffusion region.

Abstract: The present disclosure discloses a digital-to-analog conversion apparatus having a signal calibration mechanism. A conversion circuit performs digital-to-analog conversion on a digital signal to generate an output analog signal. An echo transmission circuit performs down-sampling on an echo path that the output analog signal passes through to generate an echo signal. Selected data and non-selected data included in N input parts of the input digital signal are treated as a pseudo-noise input and a signal input by N calibration circuits in an echo calibration circuit so as to be mapped by codeword offset tables and processed by groups of response coefficients to generate N calibration parts of a calibration signal. A calibration parameter calculation circuit generates offsets according to the echo signal, converges the response coefficients according to an error signal and pseudo noise transmission path information and updates the codeword offset tables accordingly.

Abstract: Interconnect structures for front-to-front stacked chips/dies and methods of fabrication thereof are disclosed herein. An exemplary system on integrated circuit (SoIC) includes a first die that is front-to-front bonded with a second die, for example, by bonding a first topmost metallization layer of a first frontside multilayer interconnect of the first die to a second topmost metallization layer of a second frontside multilayer interconnect of the second die. A through via extends partially through the first frontside multilayer interconnect of the first die, through a device layer of the first die, through a backside power rail of the first die, and through a carrier substrate. The backside power rail is between the carrier substrate and the device layer, and the backside power rail may be a portion of a backside multilayer interconnect of the first die. The through via may be connected to a redistribution layer (RDL) structure.

Abstract: A method includes forming a device die including forming integrated circuits on a semiconductor substrate; and forming a thermally conductive pillar extending into the semiconductor substrate. A cooling medium is attached over and contacting the semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillar.

Abstract: A method includes receiving a workpiece including a device layer disposed on a frontside of the workpiece, forming a frontside interconnect structure over the device layer, attaching a carrier substrate over the frontside interconnect structure, and etching from a backside of the workpiece to form first trenches and second trenches. The first trenches extend partially into the carrier substrate for a distance less than the second trenches. The method also includes forming a plurality of first conductive features in the first trenches and a plurality of second conductive features in the second trenches, forming a backside interconnect structure covering the first conductive features and the second conductive features, and thinning the carrier substrate from the frontside of the workpiece to expose the second conductive features. The first conductive features remain partially embedded in the carrier substrate.

Abstract: A method includes forming a first multilayer interconnect structure over a first side of a device layer, forming a first portion of a second multilayer interconnect structure under a second side of the device layer, forming a trench that extends through the second dielectric layer, the device layer, and the first dielectric layer, forming a conductive structure in the trench, and forming a second portion of the second multilayer interconnect structure under the first portion of the second multilayer interconnect structure. The second portion of the second multilayer interconnect structure includes patterned metal layers disposed in a third dielectric layer, and wherein one or more of the patterned metal layers are in electrical connection with the conductive structure.

Abstract: The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism is provided. A digital-to-analog conversion circuit includes conversion circuits to generate an output analog signal and echo-canceling analog signals. An echo transmission circuit processes an echo-transmitting path to generate an echo signal. An echo calibration circuit generates an output calibration signal and echo-canceling calibration signals according to an input digital circuit through calibration circuits corresponding to the conversion circuits. A calibration parameter calculating circuit generates a plurality of offsets according to an error signal of the echo signal relative to the calibration signals and path information related to the echo calibration circuit.

Abstract: The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism. A DAC circuit includes conversion circuits to generate an output analog signal and an echo-canceling analog signal. An echo transmission circuit performs signal processing on an echo path to generate an echo signal. An echo calibration circuit includes odd and even calibration circuits to perform mapping according to offset tables and perform processing according to response coefficients on odd and even input parts of an input digital signal to generate odd and even calibration parts of an echo-canceling calibration signal. A calibration parameter calculation circuit generates offsets according to an error signal between the echo signal and the echo-canceling calibration signal and path information related to the echo calibration circuit.

Abstract: The present invention discloses a digital-to-analog conversion apparatus having current source measuring mechanism. A digital-to-analog conversion circuit in turn sets one of thermo-controlled current sources as an initial current source to operate according to two specific input codewords included in an input digital signal to generate an output analog signal. The values of the output analog signal corresponding to the two specific input codewords have opposite signs and the same absolute value. An echo transmission circuit processes the output analog signal to generate an echo signal. An echo-canceling circuit processes the input digital signal according to echo-canceling coefficients to generate an echo-canceling signal and receives an error signal to converge the echo-canceling coefficients.

Abstract: The present application provides a video encoding/decoding method and apparatus. The method includes: obtaining, by a decoding end, a code stream of a unit to be decoded; determining a scanning manner and a grouping manner of the unit to be decoded, and an coding manner corresponding to each group; decoding according to the coding manner of each group to obtain one or more coefficient blocks corresponding to the unit to be decoded; and recovering one or more coefficients in each of the coefficient blocks in each group one by one according to the scanning manner of the unit to be decoded to obtain one or more reconstructed data blocks corresponding to the unit to be decoded.

Abstract: The present invention discloses a memory and a training method for neural network based on memory. The training method includes: obtaining one or more transfer functions of a memory corresponding to one or more influence factors; determining a training plan according to an ideal case and the one or more influence factors; training the neural network according to the training plan and the one or more transfer functions to obtain a plurality of weights of the trained neural network; and programming the memory according to the weights.

Abstract: A decoding method and apparatus, and an encoding method and apparatus for a picture are provided, and relate to the field of video encoding and decoding. The decoding method includes: analyzing a code stream to obtain one or more picture frames, wherein a picture frame comprises one or more coding units (CUs); determining a plurality of quantization parameter (QP) values for the picture frame, wherein a CU comprises a plurality of quantization groups (QGs), and a QG corresponds to a QP value; and decoding the picture frame based on the plurality of QP values.