Patents by Inventor Liang Wei
Liang Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12368851Abstract: Embodiments of the present disclosure relate to the field of video coding and decoding, and provide a picture decoding method, a picture coding method, and corresponding apparatuses. According to an example of the picture decoding method, a quantization parameter (QP) value of at least one pixel point is determined for any at least one pixel point indicating one pixel point or a plurality of parallel dequantized pixel points in the current coding block, the QP values of at least two pixel points among pixel points in the current coding block being different. The at least one pixel point is then dequantized according to the QP value of the at least one pixel point. The QP value of each pixel point is determined for the coding block; therefore, each pixel point can be dequantized according to the QP value of each pixel point.Type: GrantFiled: January 17, 2023Date of Patent: July 22, 2025Assignee: HANGZHOU HIKVISION DIGITAL TECHNOLOGY CO., LTD.Inventors: Liang Wei, Fangdong Chen, Li Wang
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Publication number: 20250210462Abstract: A structure according to the present disclosure includes a bottom metal feature, a semiconductor substrate disposed over the bottom metal feature, an interconnect structure disposed over the semiconductor substrate, a top metal feature over the interconnect structure, a via structure extending from a bottom surface of the top metal feature, through the interconnect structure and the semiconductor substrate, to contact a top surface of the bottom metal feature. The via structure includes a bottom portion disposed in the semiconductor substrate and a top portion disposed in the interconnect structure. The bottom portion and the top portion taper toward the top metal feature. The bottom portion includes a first tapering angle and the top portion includes a second tapering angle smaller than the first tapering angle.Type: ApplicationFiled: March 28, 2024Publication date: June 26, 2025Inventors: Ke-Gang Wen, Yu-Bey Wu, Hsin-Feng Chen, Tsung-Chieh Hsiao, Chih-Pin Chiu, Liang-Wei Wang
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Patent number: 12316362Abstract: A signal receiver and a slicer are capable of mitigating the static mismatch error of a far-end digital-to-analog converter. The slicer includes an adjustable slicing circuit and an error signal generating circuit. The adjustable slicing circuit determines which of (N+1) signal levels is corresponding to an input signal according to N slicer levels and thereby outputs an output signal, wherein the input signal is originated from the far-end digital-to-analog converter. The adjustable slicing circuit further adjusts at least some of the (N+1) signal levels according to an error signal and adjusts at least some of the N slicer levels, wherein the N is an integer greater than two. The error signal generating circuit is coupled to the adjustable slicing circuit and generates the error signal according to the input and output signals.Type: GrantFiled: September 26, 2022Date of Patent: May 27, 2025Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Hsuan-Ting Ho, Shih-Hsiung Huang, Liang-Wei Huang
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Publication number: 20250167077Abstract: A semiconductor structure includes a substrate, a device layer over the substrate, an interconnect structure over the device layer, and a first plurality of through vias and a second plurality of through vias extending through the substrate, the device layer, and the interconnect structure. The device layer includes first and second device regions. From a top view, the first device region has a first side facing and spaced apart from a second side of the second device region. From the top view, the first plurality of through vias are disposed along a third side of the first device region opposite to the first side of the first device region, the second plurality of through vias are disposed along a fourth side of the second device region opposite to the second side of the second device region. Each through via has a racetrack shape from the top view.Type: ApplicationFiled: November 17, 2023Publication date: May 22, 2025Inventors: Ke-Gang Wen, Kuan-Hsun Wang, Tsung-Chieh Hsiao, Liang-Wei Wang, Dian-Hau Chen, Hsin-Feng Chen
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Publication number: 20250157889Abstract: A method includes forming a first device die comprising forming an integrated circuit on a semiconductor substrate; and forming an interconnect structure on the semiconductor substrate. The interconnect structure has a plurality of metal layers. The method further includes bonding a second device die to the first device die, and forming gap-fill regions surrounding the second device die. In a first formation process, a first TSV is formed to penetrate through the semiconductor substrate, wherein the first TSV has a first width. In a second formation process, a second TSV is formed to penetrate through the semiconductor substrate. The second TSV has a second width different from the first width.Type: ApplicationFiled: February 20, 2024Publication date: May 15, 2025Inventors: Chih-Chieh Chang, Chih Hsin Yang, Mao-Nan Wang, Kuan-Hsun Wang, Yang-Hsin Shih, Yun-Sheng Li, Liang-Wei Wang, Dian-Hau Chen
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Publication number: 20250142799Abstract: The invention provides a layout pattern of static random-access memory (SRAM), which comprises a substrate, wherein a plurality of diffusion regions and a plurality of gate structures are located on the substrate to form a plurality of transistors, wherein the plurality of gate structures comprise a first gate structure, which has a stepped shape when viewed from a top view, and the first gate structure spans a first diffusion region and a second diffusion region to form a first access transistor (PG1), wherein the first diffusion region is adjacent to and in direct contact with the second diffusion region.Type: ApplicationFiled: December 28, 2023Publication date: May 1, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Yen Tseng, Yu-Tse Kuo, Shu-Ru Wang, Tsung-Hsun Wu, Liang-Wei Chiu, Chun-Hsien Huang
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Publication number: 20250142067Abstract: Embodiments of the present disclosure relate to the field of video coding and decoding, and provide a picture decoding method, a picture coding method, and corresponding apparatuses. According to an example of the picture decoding method, a quantization parameter (QP) value of at least one pixel point is determined for any at least one pixel point indicating one pixel point or a plurality of parallel dequantized pixel points in the current coding block, the QP values of at least two pixel points among pixel points in the current coding block being different. The at least one pixel point is then dequantized according to the QP value of the at least one pixel point. The QP value of each pixel point is determined for the coding block; therefore, each pixel point can be dequantized according to the QP value of each pixel point.Type: ApplicationFiled: January 17, 2023Publication date: May 1, 2025Inventors: Liang WEI, Fangdong CHEN, Li WANG
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Publication number: 20250132246Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a first transistor and a second transistor formed over a first side of a substrate, forming a first multi-layer interconnect (MLI) structure over the first side of the substrate, wherein the first MLI structure comprising a first plurality of metal lines and a first plurality of vias, after the forming of the first MLI structure, forming a source/drain contact directly under a source/drain feature of the first transistor, and forming a second MLI structure under the source/drain contact and under a second side of the substrate, the second side being opposite the first side, wherein the MLI structure comprises a second plurality of metal lines and a second via, a thickness of the second via is greater than a thickness of one of the first plurality of vias.Type: ApplicationFiled: October 20, 2023Publication date: April 24, 2025Inventors: Yi Ling Liu, Tsung-Chieh Hsiao, Liang-Wei Wang, Dian-Hau Chen
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Publication number: 20250099074Abstract: A medical apparatus comprises: an operating console, a limiting mechanism, and a manual release mechanism. The limiting mechanism releases the limitation on movement of the operating console in a case where a pressing force is applied to the manual release mechanism. The manual release mechanism comprises: a handle, a conversion portion, and a base portion. The handle is provided with a first guide portion. The base portion is provided with a second guide portion that cooperates with the first guide portion. The handle moves linearly in a direction substantially perpendicular to the base portion under guidance of the first guide portion and the second guide portion in a case where the pressing force is applied to the handle. Thus, a smooth linear motion of the handle can be ensured to provide a good feeling of operation, helping to improve the user experience.Type: ApplicationFiled: September 16, 2024Publication date: March 27, 2025Inventors: Yalan Yang, Mingze Yang, Fenggui Huang, Jie Wang, Fangyu Huang, Liang Wei
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Publication number: 20250087639Abstract: A method includes forming first integrated circuits on a front side of a semiconductor substrate of a first device die, forming a trench capacitor extending from a backside of the semiconductor substrate into the semiconductor substrate, and forming a first through-via and a second through-via penetrating through the semiconductor substrate. The trench capacitor is electrically coupled between the first through-via and the second through-via. A second device die is bonded to the first die. The second device die includes second integrated circuits, and power nodes of the second integrated circuits are electrically coupled to the first through-via and the second through-via.Type: ApplicationFiled: January 2, 2024Publication date: March 13, 2025Inventors: Ke-Gang Wen, Yu-Bey Wu, Tsung-Chieh Hsiao, Liang-Wei Wang, Dian-Hau Chen
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Publication number: 20250079339Abstract: Semiconductor devices having dummy regions with dummy fill structures that vary in lateral dimensions and methods for forming the semiconductor devices are provided herein. The semiconductor devices may include a through silicon via extending through a substrate of the semiconductor device, an active device in or on the substrate, and a dummy region of the substrate separating the through silicon via and the active device, the dummy region including dummy fill structures, wherein the dummy fill structures have lateral dimensions measured in a first direction from the through silicon via to the active device, wherein the lateral dimensions of the dummy fill structures varying in the first direction.Type: ApplicationFiled: August 28, 2023Publication date: March 6, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Nan Wang, Chih Hsin Yang, Liang-Wei Wang, Dian-Hau Chen
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Publication number: 20250070052Abstract: A method includes forming first nanostructures over a first region of a substrate; forming second nanostructures over a second region of the substrate; forming first gate structures around the first nanostructures; replacing the second nanostructures with isolation regions; and forming a seal ring over the substrate, wherein the seal ring is between the first region and the second region.Type: ApplicationFiled: October 24, 2023Publication date: February 27, 2025Inventors: Ke-Gang Wen, Chih Hsin Yang, Kuan-Hsun Wang, Tsung-Chieh Hsiao, Liang-Wei Wang, Dian-Hau Chen
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Publication number: 20250070064Abstract: An embodiment is a device including a first die and a substrate including a first surface and a second surface opposite the first surface. The device also includes an active device on the first surface of the substrate. The device also includes a first interconnect structure on the first surface of the substrate. The device also includes a through substrate via extending through the first interconnect structure and the substrate to the second surface of the substrate, the through substrate via being electrically coupled to metallization patterns in the first interconnect structure. The device also includes one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the through substrate via.Type: ApplicationFiled: January 3, 2024Publication date: February 27, 2025Inventors: Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang, Hsin-Feng Chen, Tsung-Chieh Hsiao, Chih Chuan Su, Dian-Hau Chen
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Publication number: 20250056781Abstract: A layout pattern of static random-access memory (SRAM) includes a substrate, a plurality of diffusion regions and a plurality of gate structures are located on the substrate, each diffusion region includes a first diffusion region, a second diffusion region, a third diffusion region, a fourth diffusion region, a fifth diffusion region, a sixth diffusion region, a seventh diffusion region and an eighth diffusion region, and each gate structure spans the plurality of diffusion regions. The plurality of gate structures include a first gate structure, the first gate structure includes a first L-shaped portion, which spans the first diffusion region and the fifth diffusion region and forms a first pull-down transistor (PD1), the first diffusion region is adjacent to and in direct contact with the fifth diffusion region.Type: ApplicationFiled: September 13, 2023Publication date: February 13, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Lin Chen, Tsung-Hsun Wu, Liang-Wei Chiu, Yao-Chin Cheng
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Publication number: 20250047292Abstract: The present disclosure discloses a digital-to-analog conversion apparatus having a signal calibration mechanism. A conversion circuit performs digital-to-analog conversion on a digital signal to generate an output analog signal. An echo transmission circuit performs down-sampling on an echo path that the output analog signal passes through to generate an echo signal. Selected data and non-selected data included in N input parts of the input digital signal are treated as a pseudo-noise input and a signal input by N calibration circuits in an echo calibration circuit so as to be mapped by codeword offset tables and processed by groups of response coefficients to generate N calibration parts of a calibration signal. A calibration parameter calculation circuit generates offsets according to the echo signal, converges the response coefficients according to an error signal and pseudo noise transmission path information and updates the codeword offset tables accordingly.Type: ApplicationFiled: July 5, 2024Publication date: February 6, 2025Inventors: SHIH-HSIUNG HUANG, HSUAN-TING HO, LIANG-WEI HUANG
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Publication number: 20250046678Abstract: A method includes receiving a workpiece including a device layer disposed on a frontside of the workpiece, forming a frontside interconnect structure over the device layer, attaching a carrier substrate over the frontside interconnect structure, and etching from a backside of the workpiece to form first trenches and second trenches. The first trenches extend partially into the carrier substrate for a distance less than the second trenches. The method also includes forming a plurality of first conductive features in the first trenches and a plurality of second conductive features in the second trenches, forming a backside interconnect structure covering the first conductive features and the second conductive features, and thinning the carrier substrate from the frontside of the workpiece to expose the second conductive features. The first conductive features remain partially embedded in the carrier substrate.Type: ApplicationFiled: January 8, 2024Publication date: February 6, 2025Inventors: Tsung-Chieh Hsiao, Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang
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Publication number: 20250046667Abstract: A method includes forming a device die including forming integrated circuits on a semiconductor substrate; and forming a thermally conductive pillar extending into the semiconductor substrate. A cooling medium is attached over and contacting the semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillar.Type: ApplicationFiled: October 6, 2023Publication date: February 6, 2025Inventors: Tsung-Chieh Hsiao, Ke-Gang Wen, Chih-Pin Chiu, Hsin-Feng Chen, Yu-Bey Wu, Liang-Wei Wang, Dian-Hau Chen
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Publication number: 20250046756Abstract: Interconnect structures for front-to-front stacked chips/dies and methods of fabrication thereof are disclosed herein. An exemplary system on integrated circuit (SoIC) includes a first die that is front-to-front bonded with a second die, for example, by bonding a first topmost metallization layer of a first frontside multilayer interconnect of the first die to a second topmost metallization layer of a second frontside multilayer interconnect of the second die. A through via extends partially through the first frontside multilayer interconnect of the first die, through a device layer of the first die, through a backside power rail of the first die, and through a carrier substrate. The backside power rail is between the carrier substrate and the device layer, and the backside power rail may be a portion of a backside multilayer interconnect of the first die. The through via may be connected to a redistribution layer (RDL) structure.Type: ApplicationFiled: January 4, 2024Publication date: February 6, 2025Inventors: Tsung-Chieh Hsiao, Yi Ling Liu, Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang
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Publication number: 20250038074Abstract: A method includes forming a first multilayer interconnect structure over a first side of a device layer, forming a first portion of a second multilayer interconnect structure under a second side of the device layer, forming a trench that extends through the second dielectric layer, the device layer, and the first dielectric layer, forming a conductive structure in the trench, and forming a second portion of the second multilayer interconnect structure under the first portion of the second multilayer interconnect structure. The second portion of the second multilayer interconnect structure includes patterned metal layers disposed in a third dielectric layer, and wherein one or more of the patterned metal layers are in electrical connection with the conductive structure.Type: ApplicationFiled: December 1, 2023Publication date: January 30, 2025Inventors: Tsung-Chieh Hsiao, Yi Ling Liu, Yun-Sheng Li, Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang, Dian-Hau Chen
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Patent number: D1081167Type: GrantFiled: January 30, 2024Date of Patent: July 1, 2025Assignee: Zhejiang Fuma Network Technology Co., Ltd.Inventor: Liang Wei