Patents by Inventor Liang Wei
Liang Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12133469Abstract: In a method of manufacturing a semiconductor device, a cell structure is formed. The cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack disposed on the bottom electrode and a hard mask layer disposed on the MTJ stack. A first insulating cover layer is formed over sidewall of the MTJ stack. A second insulating cover layer is formed over the first insulating cover layer and the hard mask layer. A first interlayer dielectric (ILD) layer is formed. The hard mask layer is exposed by etching the first ILD layer and the second insulating cover layer. A second ILD layer is formed. A contact opening is formed in the second ILD layer by patterning the second ILD layer and removing the hard mask layer. A conductive layer is formed in the contact opening so that the conductive layer contacts the MTJ stack.Type: GrantFiled: September 28, 2021Date of Patent: October 29, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Chieh Hsiao, Yu-Feng Yin, Liang-Wei Wang, Dian-Hau Chen
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Publication number: 20240355390Abstract: A storage system capable of executing data processing, includes the following elements. A first control unit of a storage device, for cooperating with a sequencer to perform a clustering process on a plurality of original sequences to obtain a plurality of read sequences, generating a plurality of read binary vectors corresponding to the read sequences, and generating a pruned filtering binary vector according to a reference sequence. A first storage module of the storage device, for storing the read binary vectors and the pruned filtering binary vector, and executing an in-memory computing (IMC) according to the read binary vectors and the pruned filtering binary vector, so as to generate a filtered cluster read set. A processing device, for executing an aligning process according to the filtered cluster read set and the reference sequence.Type: ApplicationFiled: March 5, 2024Publication date: October 24, 2024Inventors: Ming-Liang WEI, Hsiang-Pang LI, You-Kai ZHENG, Chia-Lin YANG
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Publication number: 20240355672Abstract: Embodiments of the present disclosure provide methods of forming a RDL structure with a flat passivation surface. Some embodiments provide a stop layer for chemical mechanical polishing disposed under a passivation layer. Some embodiments provide an extra thickness of passivation deposition and a sacrificial passivation layer for passivation polishing. Some embodiments provide a modified RDL pattern by inserting dummy pattern objects to adjust pattern density.Type: ApplicationFiled: August 17, 2023Publication date: October 24, 2024Inventors: Zhen De MA, Chih-Pin CHIU, Lee-Wen HSU, Liang-Wei WANG, Dian-Hau CHEN
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Patent number: 12113587Abstract: A digital-to-analog converter circuit generates an analog transmitted signal according to a digital transmitted signal. A first echo canceller circuit generates a first echo cancelling signal according to the digital transmitted signal. A processor circuit generates an analog processed signal according to the analog transmitted signal, the first echo cancelling signal, and a received signal. An analog-to-digital converter circuit generates a digital value according to the analog processed signal and two slicer levels of a plurality of slicer levels. A storage circuit stores a look-up table. The look-up table records an offset value corresponding to the digital value. The storage circuit further outputs a first output signal according to the digital value and the offset value. The offset value is updated according to an error value associated with the first output signal.Type: GrantFiled: October 21, 2021Date of Patent: October 8, 2024Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Hsuan-Ting Ho, Liang-Wei Huang, Wei-Chiang Hsu, Wei-Jyun Wang
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Patent number: 12108773Abstract: The present invention relates to a method of producing a non-dairy frozen confectionery, the method comprising the steps of: 1) providing a grain based ingredient mix comprising plant syrup and having 20-40 wt. % solids, pasteurizing the grain based ingredient mix, fermenting the pasteurized grain based mix with a culture, and cooling the fermented grain ingredient based ingredient mix, and 2) providing a nut and/or seed based ingredient mix comprising 40-60 wt. % solids and 3) combining it with the cooled fermented grain based ingredient mix, and freezing while optionally aerating the combined grain and nut and/or seed based mixes, to form a frozen confectionery. The invention also relates to a non-dairy frozen confectionery comprising 3-20 wt. % grain fermented with Streptococcus thermophilus, and 4-40 wt. % seed and/or nuts.Type: GrantFiled: December 2, 2019Date of Patent: October 8, 2024Assignee: Societe des Produits Nestle S.A.Inventors: Juan Du, Christoph Josef Bolten, Liang Wei Wilson Lee, Nilesh Desai
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Publication number: 20240329113Abstract: A redistribution structure is provided. A redistribution structure according to the present disclosure includes a first dielectric layer, a mesh metal feature disposed in the first dielectric layer and including a base portion and a frame portion surrounding the base portion, a second dielectric layer disposed over the first dielectric layer and the mesh metal feature, a redistribution feature disposed over the second dielectric layer, a passivation structure disposed over the redistribution feature and the second dielectric layer, a pad opening extending through the passivation structure to expose a top surface of the redistribution feature. The redistribution feature includes a plurality of contact vias that extend through the second dielectric layer to land on the frame portion of the mesh metal feature.Type: ApplicationFiled: July 25, 2023Publication date: October 3, 2024Inventors: Chih-Pin Chiu, Zhen De Ma, Lee-Wen Hsu, Liang-Wei Wang, Dian-Hau Chen
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Patent number: 12100605Abstract: A gas purge device includes a first nozzle and a gas gate. The first nozzle is coupled to a front-opening unified pod (FOUP) through a first port of the FOUP. The gas gate is coupled to the first nozzle via a first pipe. The gas gate includes a first mass flow controller (MFC), a second MFC, and a first switch unit. The first MFC is configured to control a first flow of a first gas. The second MFC is configured to control a second flow of a second gas. The first switch unit is coupled to the first MFC and the second MFC, and is configured to provide the first gas to the first nozzle through the first pipe or receive the second gas from the first nozzle through the first pipe according to a process configuration.Type: GrantFiled: October 19, 2023Date of Patent: September 24, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Meng-Liang Wei, Sun-Fu Chou
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Publication number: 20240312840Abstract: Through via structures and methods of fabrication thereof are disclosed herein. An exemplary method includes forming a trench that extends through an insulation layer and into a substrate. The substrate has a first side (e.g., frontside) and a second side (e.g., backside). The insulation layer is disposed over the first side of the substrate. The method includes filling the trench with a dielectric material and performing a thinning process on the second side of the substrate that exposes the dielectric material. After the thinning process and removing the dielectric material from the trench, the method includes forming an electrically conductive structure (e.g., a barrier liner that wraps an electrically conductive plug) in the trench that extends through the substrate from the first side to the second side. A portion of the barrier liner that forms a top of the electrically conductive structure is disposed in the insulation layer.Type: ApplicationFiled: July 10, 2023Publication date: September 19, 2024Inventors: Lee-Wen Hsu, Liang-Wei Wang, Chih-Pin Chiu, Dian-Hau Chen
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Patent number: 12088825Abstract: Decoding methods and encoding methods based on an adaptive intra refresh mechanism and related devices are provided. In one aspect, a decoding method includes: receiving a bit stream of a current frame; and determining whether the current frame supports an adaptive intra refresh technology. The determining comprises one of: if there is extension data in the bit stream of the current frame and the extension data carries an adaptive intra refresh video extension identifier (ID), obtaining virtual boundary position information carried in the extension data, and determining whether the current frame supports an adaptive intra refresh technology based on the virtual boundary position information; or if there is no adaptive intra refresh video extension ID in the extension data in the bit stream of the current frame, determining that the current frame does not support the adaptive intra refresh technology.Type: GrantFiled: March 10, 2022Date of Patent: September 10, 2024Assignee: HANGZHOU HIKVISION DIGITAL TECHNOLOGY CO., LTD.Inventors: Liang Wei, Fangdong Chen, Li Wang
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Publication number: 20240282837Abstract: A first conductive pad disposed over a first side of a substrate in a first direction. A second conductive pad is disposed over a second side of the substrate in the first direction. A through-substrate via (TSV) extends into the substrate in the first direction. The TSV is disposed between the first conductive pad and the second conductive pad in the first direction. An air liner disposed between the TSV and the substrate in a second direction different from the first direction.Type: ApplicationFiled: June 15, 2023Publication date: August 22, 2024Inventors: Kuan-Hsun Wang, Tsung-Chieh Hsiao, Chih Hsin Yang, Liang-Wei Wang, Dian-Hau Chen
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Patent number: 12068753Abstract: The present invention discloses a signal gain tuning circuit having adaptive mechanism. An amplifier receives an analog signal to generate a tuned analog signal to an ADC circuit to further generate a digital signal. A gain control capacitor array and the amplifier together determine a gain of the tuned analog signal. The control circuit receives an actual level of the digital signal to determine an offset of the digital signal and an estimated level to generate a tuning control signal. Each of coarse-tuning capacitors of a coarse-tuning capacitor array corresponds to a first tuning amount relative to a maximal gain. Each of fine-tuning capacitors of a fine-tuning capacitor array corresponds to a second tuning amount relative to the maximal gain. A tuning capacitor enabling combination of the coarse-tuning and fine-tuning capacitor arrays are determined according to the tuning control signal to tune the gain and decrease the offset.Type: GrantFiled: September 15, 2022Date of Patent: August 20, 2024Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Yun-Tse Chen, Hsuan-Ting Ho, Liang-Wei Huang, Tzung-Hua Tsai
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Patent number: 12063790Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first source/drain feature and a second source/drain feature, a first metal line disposed in a first dielectric layer and electrically connected to the first source/drain feature, a second metal line disposed in the first dielectric layer and electrically connected to the second source/drain feature, and a first memory element disposed over the first dielectric layer and electrically connected to the first source/drain feature by way of the first metal line. A width of the first metal line is different from a width of the second metal line. By changing the widths of the first metal line and the second metal line, a source line series resistance of a semiconductor device can be advantageously reduced without changing a pitch of two metal lines.Type: GrantFiled: August 30, 2021Date of Patent: August 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Fan Huang, Wen-Chiung Tu, Liang-Wei Wang, Dian-Hau Chen, Yen-Ming Chen
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Patent number: 12062070Abstract: The present disclosure describes a system that attempts to reconcile diverse goals and re-cast the goals into something that is quantifiable and optimizable. One way to reconcile diverse goals is by converting these “constraints”—with the huge problems of feasibility—into errors that can be minimized. This disclosure also presents solutions for rate constraints which previously have not been dealt with. The resulting system enables advertisers to dynamically adjust their campaign based on the needs of the moment. Such a system can have advantages in terms of controllability, smoothness, as well as avoiding hard stop conditions that plague the constraint-based approach. In order to achieve this result, solutions are presented for problems of pacing, viewability prediction, and most particularly, error minimization.Type: GrantFiled: November 2, 2020Date of Patent: August 13, 2024Assignee: ADAP.TV, INC.Inventors: Brendan Kitts, Garrett James Badeau, Michael Krishnan, Yongbo Zeng, Ishadulta Yadav, Ruofeng Chen, Andrew George Potter, Liang Wei, Ethan James Thornburg, Sergey Tolkachov
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Publication number: 20240266334Abstract: An integrated semiconductor device is provided. The integrated semiconductor device includes a first semiconductor structure having a first IC, and a second semiconductor structure stacked above the first semiconductor structure and having a second IC. The second semiconductor structure has a first surface facing the first semiconductor structure and a second surface facing away from the first semiconductor structure. The integrated semiconductor device also includes a thermal dissipation structure having a first portion partially through the first IC and a second portion fully through the second semiconductor structure and exposed at the second surface of the second semiconductor structure. The second portion may be outside of the second IC.Type: ApplicationFiled: February 7, 2023Publication date: August 8, 2024Inventors: Ke-Gang Wen, Liang-Wei Wang, Dian-Hau Chen, Tsung-Chieh Hsiao
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Patent number: 12057856Abstract: A calibrating device can mitigate the static mismatch error of a digital-to-analog converter (DAC), and includes a digital code generating circuit, the DAC, an analog-to-digital converter (ADC), a filter circuit, an indicating circuit, and a statistical circuit. The digital code generating circuit generates a digital code of N digital codes. The DAC generates an analog signal corresponding to one of N signal levels according to the digital code. The ADC generates a digital signal according to the analog signal. The filter circuit generates a gradient value according to the difference between the digital code and the digital signal. The indicating circuit generates a selection signal according to the digital code. The statistical circuit learns from the selection signal that the gradient value is corresponding to a Kth digital code of the N digital codes, and determines whether the Kth digital code should be adjusted according to the gradient value.Type: GrantFiled: September 28, 2022Date of Patent: August 6, 2024Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Hsuan-Ting Ho, Shih-Hsiung Huang, Liang-Wei Huang
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Publication number: 20240250842Abstract: The present disclosure provides monitoring device, electronic device control system and method. The electronic device control system includes the monitoring device and at least one electronic device. The monitoring device includes lens component, light emitting component, communication circuit and control circuit. The lens component is configured to capture image. The communication circuit is configured to establish wireless connection with mobile device, and is configured to receive first control data from the mobile device via the wireless connection. The control circuit is electrically coupled to the lens component, the light emitting component and the communication circuit, and is configured to control the light emitting component to emit first optical control signal to the at least one electronic device according to the first control data, so that the at least one electronic device performs first action according to the first optical control signal.Type: ApplicationFiled: July 20, 2023Publication date: July 25, 2024Inventor: Chia-Liang WEI
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Patent number: 12028606Abstract: A system for remotely controlling microscopic machinery and a method thereof are provided. The system includes at least one local device and a remote host for sending a control command thereto. A microslide is placed on a microscopic camera device in the local device, and the microscopic camera device captures an image of the microslide according to a capture command in the control command. The local device transmits the image to the remote host in a video format. A motorized stage moves to a next preset position according to a movement command in the control command to capture another image of the microslide. The steps of capturing and transmitting the image and the step of moving are repeated until the microslide is captured completely. The invention can solve the problem of time delay when the image captured by the remote control microscopic camera device is displayed.Type: GrantFiled: November 15, 2022Date of Patent: July 2, 2024Assignee: V5MED INC.Inventors: Tzu-Kuei Shen, Kuo-Tung Hung, Guang-Hao Suen, Liang-Wei Sheu
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Patent number: 12027399Abstract: The present disclosure provides a gas purge device and a gas purge method for purging a wafer container to clean wafers. The gas purge device includes a first nozzle and a gas gate. The first nozzle is coupled to a front-opening unified pod (FOUP) through a first port of the FOUP. The gas gate is coupled to the first nozzle via a first pipe. The gas gate includes a first mass flow controller (MFC), a second MFC, and a first switch unit. The first MFC is configured to control a first flow of a first gas. The second MFC is configured to control a second flow of a second gas. The first switch unit is coupled to the first MFC and the second MFC, and is configured to provide the first gas to the first nozzle through the first pipe or receive the second gas from the first nozzle through the first pipe according to a process configuration.Type: GrantFiled: October 22, 2020Date of Patent: July 2, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Meng-Liang Wei, Sun-Fu Chou
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Publication number: 20240215261Abstract: A semiconductor package includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first semiconductor substrate, a first bonding structure bonded to the second integrated circuit, a ferromagnetic layer surrounding the first bonding structure, and a memory cell between the first semiconductor substrate and the first bonding structure.Type: ApplicationFiled: March 6, 2024Publication date: June 27, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiang-Ku Shen, Ku-Feng Lin, Liang-Wei Wang, Dian-Hau Chen
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Publication number: 20240212139Abstract: An automatic calculation method of gray-to-white-matter ratio for head computed tomography of patients with cardiac arrest is disclosed and includes an image registration step, a K-means segmentation step, a segmentation refinement step and a GWR calculation step. Measure the gray-white-matter ratio through brain computed tomography early after cardiac arrest to automatically identify the corpus callosum, caudate nucleus, putamen, and posterior branch of the internal brain cyst. It is a 3D three-dimensional structure rather than a manually selected flat circular area to evaluate the effectiveness of predicting neurological prognosis at discharge.Type: ApplicationFiled: December 21, 2023Publication date: June 27, 2024Applicants: NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN UNIVERSITY HOSPITALInventors: Chien-Hua HUANG, Chien-Yu CHI, Liang-Wei WANG, Yu-Jen SU, Weichung WANG, Hsin-Han TSAI, Cheyu HSU