Patents by Inventor Liang Wei

Liang Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12003249
    Abstract: The present invention discloses a DAC method having signal calibration mechanism used in a DAC circuit having thermometer-controlled current sources generating an output analog signal according to a total current thereof and a control circuit. Current offset values of the current sources are retrieved. The current offset values are sorted to generate a turn-on order, in which the current offset values are separated into current offset groups according to the turn-on order, the signs of each neighboring two groups being opposite such that the current offset values cancel each other when the current sources turn on according to the turn-on order to keep an absolute value of a total offset not larger than a half of a largest absolute value of the current offset values. The current sources are turned on based on the turn-on order according to a thermal code included in an input digital signal.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: June 4, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kai-Yue Lin, Hsuan-Ting Ho, Liang-Wei Huang, Chi-Hsi Su
  • Patent number: 12004431
    Abstract: A semiconductor device includes a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Chieh Hsiao, Po-Sheng Lu, Wei-Chih Wen, Liang-Wei Wang, Yu-Jen Wang, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 11978270
    Abstract: An AI-assisted automatic labeling system and a method thereof are disclosed. The method comprises steps: selecting images from microscopic images as candidate images, using a pre-labeling module to automatically label cells in the candidate images, and dividing the labeled images into training data and verification data; using a training module and the training data to train a basic model; using a verification module to verify and modify the basic model, wherein the verification module respectively verifies at least one cell area and at least one background area of the verification data to converge the basic model and form an automatic labeling model; using the automatic labeling model to automatically label cells in redundant images of the microscopic images. The basic model trained by the present invention can use few labeled images to perform regressive training and verification and then automatically labels the redundant images accurately and efficiently.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: May 7, 2024
    Assignee: V5med Inc.
    Inventors: Tzu-Kuei Shen, Chien Ting Yang, Guang-Hao Suen, Linda Siana, Liang-Wei Sheu
  • Publication number: 20240145344
    Abstract: A via structure, a semiconductor structure, and methods for forming the via structure and the semiconductor structure are presented. A via structure includes a first conductive portion through an interconnect structure, a second conductive portion through a substrate and in contact with the first conductive portion, and a liner layer. The liner layer is between the first conductive portion and the interconnect structure, and between the second conductive portion and the substrate. The liner layer includes a portion extending parallel to a surface of the substrate.
    Type: Application
    Filed: February 22, 2023
    Publication date: May 2, 2024
    Inventors: Tsung-Chieh Hsiao, Liang-Wei Wang, Dian-Hau Chen
  • Publication number: 20240145435
    Abstract: Some implementations described herein include systems and techniques for fabricating a multi-dimension through silicon via structure in a three-dimensional integrated circuit device. The multi-dimension through silicon via structure includes a first columnar structure having a first width and a second columnar structure including a second width that is greater relative to the first width. The first columnar structure may include a low electrical capacitance and be configured for electrical signaling within the three-dimensional integrated circuit device. The second columnar structure may be configured to provide power to integrated circuitry of the three-dimensional integrated circuit device and also be configured to conduct heat through the three-dimensional integrated circuit device for thermal management of the three-dimensional integrated circuit device. Additionally, a pattern including the second columnar structure may be used for alignment purposes.
    Type: Application
    Filed: April 26, 2023
    Publication date: May 2, 2024
    Inventors: Ke-Gang WEN, Tsung-Chieh HSIAO, Liang-Wei WANG, Dian-Hau CHEN
  • Publication number: 20240120257
    Abstract: An integrated circuit (IC) device includes a substrate. The IC device includes a multi-layer interconnect structure disposed over a first side of the substrate. The multi-layer interconnect structure includes a plurality of metal layers. The IC device includes a first portion of a through-substrate via (TSV) disposed over the first side of the substrate. The first portion of the TSV includes a plurality of conductive components belonging to the plurality of metal layers of the multi-layer interconnect structure. The IC device includes a second portion of the TSV that extends vertically through the substrate from the first side to a second side opposite the first side. The second portion of the TSV is electrically coupled to the first portion of the TSV.
    Type: Application
    Filed: March 30, 2023
    Publication date: April 11, 2024
    Inventors: Tsung-Chieh Hsiao, Ke-Gang Wen, Liang-Wei Wang, Dian-Hau Chen
  • Publication number: 20240114239
    Abstract: A system for remotely controlling microscopic machinery and a method thereof are provided. The system includes at least one local device and a remote host for sending a control command thereto. A microslide is placed on a microscopic camera device in the local device, and the microscopic camera device captures an image of the microslide according to a capture command in the control command. The local device transmits the image to the remote host in a video format. A motorized stage moves to a next preset position according to a movement command in the control command to capture another image of the microslide. The steps of capturing and transmitting the image and the step of moving are repeated until the microslide is captured completely. The invention can solve the problem of time delay when the image captured by the remote control microscopic camera device is displayed.
    Type: Application
    Filed: November 15, 2022
    Publication date: April 4, 2024
    Applicant: V5 TECHNOLOGIES CO., LTD.
    Inventors: TZU-KUEI SHEN, KUO-TUNG HUNG, GUANG-HAO SUEN, LIANG-WEI SHEU
  • Patent number: 11950432
    Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first semiconductor substrate, a first bonding structure and a memory cell. The second semiconductor device is stacked over the first semiconductor device. The second semiconductor device includes a second semiconductor substrate, a second bonding structure in a second dielectric layer and a peripheral circuit between the second semiconductor substrate and the second bonding structure. The first bonding structure and the second bonding structure are bonded and disposed between the memory cell and the peripheral circuit, and the memory cell and the peripheral circuit are electrically connected through the first bonding structure and the second bonding structure.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Ku Shen, Ku-Feng Lin, Liang-Wei Wang, Dian-Hau Chen
  • Publication number: 20240092746
    Abstract: Provided herein are opioid receptor modulators and pharmaceutical compositions comprising said compounds.
    Type: Application
    Filed: February 13, 2023
    Publication date: March 21, 2024
    Inventors: Julio Cesar MEDINA, Alok NERURKAR, Corinne SADLOWSKI, Frederick SEIDL, Heng CHENG, Jason DUQUETTE, John LEE, Martin HOLAN, Pingyu DING, Xiaodong WANG, Tien WIDJAJA, Thomas NGUYEN, Ulhas BHATT, Yihong LI, Zhi-liang WEI
  • Patent number: 11937515
    Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Hsiang-Ku Shen, Liang-Wei Wang, Chen-Chiu Huang, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 11923866
    Abstract: The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: March 5, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsuan-Ting Ho, Shih-Hsiung Huang, Liang-Wei Huang
  • Publication number: 20240062563
    Abstract: A system and a method for determining characteristic cells based on image recognition. In the method, a scanning device capturing a full image of the microslide; a host selecting images that comprise stained blocks from the full image; the host sequentially performing image recognition to recognize stained cells of the images, and determining whether the stained cells comprise the characteristic cells with an AI model; and selecting interested images from the images that comprise the characteristic cells, transforming the coordinate system of the interested images into the original coordinate system of the full image, and employing the scanning device to capture the interested images along the Z axis of the original coordinate system of the full image, thereby obtaining and outputting sets of pictures. The present invention can quickly determine whether there are characteristic cells in the tissue under test, so as to provide a diagnostic reference for doctors.
    Type: Application
    Filed: December 27, 2022
    Publication date: February 22, 2024
    Applicants: V5 TECHNOLOGIES CO., LTD., Taipei Veterans General Hospital
    Inventors: TZU-KUEI SHEN, LINDA SIANA, GUANG-HAO SUEN, LIANG-WEI SHEU, CHIEN-TING YANG, Yuh-Min Chen, Heng-sheng Chao, Chung-Wei Chou, Tsu-Hui Shiao, Yi-Han Hsiao, Chi-Lu Chiang
  • Publication number: 20240047251
    Abstract: A gas purge device includes a first nozzle and a gas gate. The first nozzle is coupled to a front-opening unified pod (FOUP) through a first port of the FOUP. The gas gate is coupled to the first nozzle via a first pipe. The gas gate includes a first mass flow controller (MFC), a second MFC, and a first switch unit. The first MFC is configured to control a first flow of a first gas. The second MFC is configured to control a second flow of a second gas. The first switch unit is coupled to the first MFC and the second MFC, and is configured to provide the first gas to the first nozzle through the first pipe or receive the second gas from the first nozzle through the first pipe according to a process configuration.
    Type: Application
    Filed: October 19, 2023
    Publication date: February 8, 2024
    Inventors: MENG-LIANG WEI, SUN-FU CHOU
  • Publication number: 20240048726
    Abstract: Decoding methods and encoding methods based on an adaptive intra refresh mechanism and related devices are provided. In one aspect, a decoding method includes: receiving a bit stream of a current frame; and determining whether the current frame supports an adaptive intra refresh technology. The determining comprises one of if there is extension data in the bit stream of the current frame and the extension data carries an adaptive intra refresh video extension identifier (ID), obtaining virtual boundary position information carried in the extension data, and determining whether the current frame supports an adaptive intra refresh technology based on the virtual boundary position information; or if there is no adaptive intra refresh video extension ID in the extension data in the bit stream of the current frame, determining that the current frame does not support the adaptive intra refresh technology.
    Type: Application
    Filed: March 10, 2022
    Publication date: February 8, 2024
    Inventors: Liang WEI, Fangdong CHEN, Li WANG
  • Patent number: 11894856
    Abstract: The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: February 6, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsuan-Ting Ho, Liang-Wei Huang, Yun-Chih Tsai, Chia-Lin Chang
  • Publication number: 20240032166
    Abstract: The present disclosure provides a full-spectrum LED color management system based on RGBWCLA seven-color integration, including an LED lamp; an aluminum substrate inside the LED lamp; a seven-color-integrated full-spectrum integrated LED light source arranged on the aluminum substrate, a lens fixed to the aluminum substrate, a color processing operation chip, a data mining extensions (DMX) communication module, a color control module, a high-precision spectral brightness detector and a color calculation software computer device. In the foregoing mode, the full-spectrum LED color management system implements the following: the seven-color lamp implements a change in simulated blackbody curve correlated color temperature (CCT) from 1,800 K to 8,000 K; the seven-color lamp implements full-spectrum output of white light, and has a color rendering index Ra of 95 or above and R9>90; and the seven-color lamp implements 240% REC.709 color gamut coverage.
    Type: Application
    Filed: October 25, 2022
    Publication date: January 25, 2024
    Inventors: Yinghui Lu, Liang Wei, Zhangjun Liu
  • Publication number: 20240020994
    Abstract: A system and a method for cell statistics based on image recognition is disclosed. A microscope captures the full image of a microslide, selects an interest region from the full image, and divides the region into sub-regions. A camera scans and transits the sub-regions to a host. The host performs image recognition on the scanned images to recognize various cells, and accumulates the number of the various cells in each of the scanned images to obtain a cell ratio of each type of the cells. When the number is accumulated and a difference among the cell ratios of the N consecutive scanned images is less than a preset value, the host stops scanning the remains of the sub-regions and outputs the cell ratio of each type of the presently-accumulated cells. The method can obtain various cell ratios of tissue samples for diagnosis.
    Type: Application
    Filed: September 23, 2022
    Publication date: January 18, 2024
    Applicant: V5 TECHNOLOGIES CO., LTD.
    Inventors: LINDA SIANA, GUANG-HAO SUEN, LIANG-WEI SHEU, CHIEN-TING YANG
  • Patent number: 11853890
    Abstract: Provided is an operation method for a memory device, the memory device being used for implementing an Artificial Neural Network (ANN). The operation method includes: reading from the memory device a weight matrix of a current layer of a plurality of layers of the ANN to extract a plurality of neuro values; determining whether to perform calibration; when it is determined to perform calibration, recalculating and updating a mean value and a variance value of the neuro values; and performing batch normalization based on the mean value and the variance value of the neuro values.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 26, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chao-Hung Wang, Yu-Hsuan Lin, Ming-Liang Wei, Dai-Ying Lee
  • Patent number: 11855669
    Abstract: A method for cancelling radio frequency interference (RFI) and a communication system thereof are provided. In the communication system, digital signals of a frequency domain are converted from analog signals and received by the communication system generally carry RFI, and the signals are processed by an equalizer and a far-end crosstalk canceller. Then, for preventing erroneous signals from forming due to an occurrence of a notch, masking parameters applied to the equalizer and the far-end crosstalk canceller are modified for not processing frequency bands that are RFI-affected. The frequency bands can be ignored by masking corresponding bins in the frequency domain after a fast Fourier transformation. The signals processed by the equalizer and the far-end crosstalk canceller are then outputted to an RFI canceller, and the signals with RFI cancellation can be obtained.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: December 26, 2023
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Po-Hsiu Hsiao, Liang-Wei Huang
  • Publication number: 20230395586
    Abstract: A semiconductor structure and processes of forming the same are provided. A semiconductor structure according to the present disclosure includes a first die having a front surface and a back surface and a second die bonded to the back surface of the first die. The first die includes a plurality of trenches adjacent the back surface and the plurality of trenches are filled with a liquid.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventors: Tsung-Chieh Hsiao, Chih Hsin Yang, Liang-Wei Wang, Dian-Hau Chen