Abstract: The present disclosure discloses a digital-to-analog conversion apparatus having a signal calibration mechanism. A conversion circuit performs digital-to-analog conversion on a digital signal to generate an output analog signal. An echo transmission circuit performs down-sampling on an echo path that the output analog signal passes through to generate an echo signal. Selected data and non-selected data included in N input parts of the input digital signal are treated as a pseudo-noise input and a signal input by N calibration circuits in an echo calibration circuit so as to be mapped by codeword offset tables and processed by groups of response coefficients to generate N calibration parts of a calibration signal. A calibration parameter calculation circuit generates offsets according to the echo signal, converges the response coefficients according to an error signal and pseudo noise transmission path information and updates the codeword offset tables accordingly.

Abstract: A method includes forming a device die including forming integrated circuits on a semiconductor substrate; and forming a thermally conductive pillar extending into the semiconductor substrate. A cooling medium is attached over and contacting the semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillar.

Abstract: Interconnect structures for front-to-front stacked chips/dies and methods of fabrication thereof are disclosed herein. An exemplary system on integrated circuit (SoIC) includes a first die that is front-to-front bonded with a second die, for example, by bonding a first topmost metallization layer of a first frontside multilayer interconnect of the first die to a second topmost metallization layer of a second frontside multilayer interconnect of the second die. A through via extends partially through the first frontside multilayer interconnect of the first die, through a device layer of the first die, through a backside power rail of the first die, and through a carrier substrate. The backside power rail is between the carrier substrate and the device layer, and the backside power rail may be a portion of a backside multilayer interconnect of the first die. The through via may be connected to a redistribution layer (RDL) structure.

Abstract: A method includes forming a first multilayer interconnect structure over a first side of a device layer, forming a first portion of a second multilayer interconnect structure under a second side of the device layer, forming a trench that extends through the second dielectric layer, the device layer, and the first dielectric layer, forming a conductive structure in the trench, and forming a second portion of the second multilayer interconnect structure under the first portion of the second multilayer interconnect structure. The second portion of the second multilayer interconnect structure includes patterned metal layers disposed in a third dielectric layer, and wherein one or more of the patterned metal layers are in electrical connection with the conductive structure.

Abstract: The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism is provided. A digital-to-analog conversion circuit includes conversion circuits to generate an output analog signal and echo-canceling analog signals. An echo transmission circuit processes an echo-transmitting path to generate an echo signal. An echo calibration circuit generates an output calibration signal and echo-canceling calibration signals according to an input digital circuit through calibration circuits corresponding to the conversion circuits. A calibration parameter calculating circuit generates a plurality of offsets according to an error signal of the echo signal relative to the calibration signals and path information related to the echo calibration circuit.

Abstract: The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism. A DAC circuit includes conversion circuits to generate an output analog signal and an echo-canceling analog signal. An echo transmission circuit performs signal processing on an echo path to generate an echo signal. An echo calibration circuit includes odd and even calibration circuits to perform mapping according to offset tables and perform processing according to response coefficients on odd and even input parts of an input digital signal to generate odd and even calibration parts of an echo-canceling calibration signal. A calibration parameter calculation circuit generates offsets according to an error signal between the echo signal and the echo-canceling calibration signal and path information related to the echo calibration circuit.

Abstract: The present invention discloses a digital-to-analog conversion apparatus having current source measuring mechanism. A digital-to-analog conversion circuit in turn sets one of thermo-controlled current sources as an initial current source to operate according to two specific input codewords included in an input digital signal to generate an output analog signal. The values of the output analog signal corresponding to the two specific input codewords have opposite signs and the same absolute value. An echo transmission circuit processes the output analog signal to generate an echo signal. An echo-canceling circuit processes the input digital signal according to echo-canceling coefficients to generate an echo-canceling signal and receives an error signal to converge the echo-canceling coefficients.

Abstract: The present application provides a video encoding/decoding method and apparatus. The method includes: obtaining, by a decoding end, a code stream of a unit to be decoded; determining a scanning manner and a grouping manner of the unit to be decoded, and an coding manner corresponding to each group; decoding according to the coding manner of each group to obtain one or more coefficient blocks corresponding to the unit to be decoded; and recovering one or more coefficients in each of the coefficient blocks in each group one by one according to the scanning manner of the unit to be decoded to obtain one or more reconstructed data blocks corresponding to the unit to be decoded.

Abstract: The present invention discloses a memory and a training method for neural network based on memory. The training method includes: obtaining one or more transfer functions of a memory corresponding to one or more influence factors; determining a training plan according to an ideal case and the one or more influence factors; training the neural network according to the training plan and the one or more transfer functions to obtain a plurality of weights of the trained neural network; and programming the memory according to the weights.

Abstract: A decoding method and apparatus, and an encoding method and apparatus for a picture are provided, and relate to the field of video encoding and decoding. The decoding method includes: analyzing a code stream to obtain one or more picture frames, wherein a picture frame comprises one or more coding units (CUs); determining a plurality of quantization parameter (QP) values for the picture frame, wherein a CU comprises a plurality of quantization groups (QGs), and a QG corresponds to a QP value; and decoding the picture frame based on the plurality of QP values.

Abstract: One aspect of the present disclosure pertains to a method. The method includes receiving a first circuit structure having semiconductor devices, an interconnect structure, first feedthrough vias, top metal lines, redistribution vias, and bond pads. The method includes dicing the first circuit structure to form a top die having a top semiconductor device. The method includes forming a stacked integrated circuit (IC) structure by bonding the top die to a second circuit structure, the second circuit structure having second semiconductor devices, a second interconnect structure, second redistribution vias, and second bond pads. The method includes forming IC top metal lines over the first feedthrough vias, forming an IC passivation layer over the IC top metal lines, forming metal-insulator-metal (MIM) capacitor structures in the IC passivation layer, and forming IC redistribution vias penetrating through the MIM capacitor structures and the IC passivation layer to land on the IC top metal lines.

Abstract: Provided herein are opioid receptor modulators and pharmaceutical compositions comprising said compounds.

Abstract: Semiconductor structures and methods for forming the same that include a through substrate via. Sacrificial semiconductor structures (e.g., fins) are formed with metal gate structures in a through via region. An opening is formed through BEOL layers to expose the metal gates, which may then be removed. A liner layer is formed on sidewalls of the opening including on semiconductor structures extending from the substrate. The opening is then extended into the substrate and a through substrate via is formed from the extended opening.

Abstract: In a method of manufacturing a semiconductor device, a cell structure is formed. The cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack disposed on the bottom electrode and a hard mask layer disposed on the MTJ stack. A first insulating cover layer is formed over sidewall of the MTJ stack. A second insulating cover layer is formed over the first insulating cover layer and the hard mask layer. A first interlayer dielectric (ILD) layer is formed. The hard mask layer is exposed by etching the first ILD layer and the second insulating cover layer. A second ILD layer is formed. A contact opening is formed in the second ILD layer by patterning the second ILD layer and removing the hard mask layer. A conductive layer is formed in the contact opening so that the conductive layer contacts the MTJ stack.

Abstract: Decoding methods and encoding methods based on an adaptive intra refresh mechanism and related devices are provided. In one aspect, a decoding method includes: receiving a bit stream of a current frame; and determining whether the current frame supports an adaptive intra refresh technology. The determining comprises one of: if there is extension data in the bit stream of the current frame and the extension data carries an adaptive intra refresh video extension identifier (ID), obtaining virtual boundary position information carried in the extension data, and determining whether the current frame supports an adaptive intra refresh technology based on the virtual boundary position information; or if there is no adaptive intra refresh video extension ID in the extension data in the bit stream of the current frame, determining that the current frame does not support the adaptive intra refresh technology.

Abstract: A semiconductor structure includes a third metal layer immediately above a second metal layer that is over a first metal layer. The second metal layer includes magnetic tunneling junction (MTJ) devices in a memory region and a first conductive feature in a logic region. Each MTJ device includes a bottom electrode and an MTJ stack over the bottom electrode. The third metal layer includes a first via electrically connecting to the first conductive feature, and a slot via over and electrically connecting to the MTJ stack of the MTJ devices. The slot via occupies space extending continuously and laterally from a first one to a last one of the MTJ devices. The first via is as thin as or thinner than the slot via. The third metal layer further includes second and third conductive features electrically connecting to the first via and the slot via, respectively.

Abstract: A method of forming a semiconductor device includes following steps. A sacrificial layer is formed in an opening of a substrate. A first doped region is formed in the opening over the sacrificial layer. The substrate is flipped. A portion of the substrate is removed to expose the sacrificial layer. The sacrificial layer is replaced with a first contact.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming an opening in a semiconductor body, and the semiconductor body is p-type doped. The method also includes introducing n-type dopants into the semiconductor body to form a modified portion near the opening, and the modified portion is p-type doped. The method further includes forming a dielectric layer along the sidewalls and the bottom of the opening. In addition, the method includes forming a conductive structure over the dielectric layer to fill the opening.

Abstract: Semiconductor structures and methods for forming the same that include a through substrate via. Sacrificial gate structures are formed concurrently with active gate structures, the sacrificial gate structures being disposed in a through via region of the substrate. The sacrificial gate structures are subsequently removed from the substrate and dielectric material formed in their place. The through substrate via extends through the dielectric material.

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first source/drain feature and a second source/drain feature, a first metal line disposed in a first dielectric layer and electrically connected to the first source/drain feature, a second metal line disposed in the first dielectric layer and electrically connected to the second source/drain feature, and a first memory element disposed over the first dielectric layer and electrically connected to the first source/drain feature by way of the first metal line. A width of the first metal line is different from a width of the second metal line. By changing the widths of the first metal line and the second metal line, a source line series resistance of a semiconductor device can be advantageously reduced without changing a pitch of two metal lines.