Abstract: An inhibitor of a prostate specific membrane antigen and a pharmaceutical use thereof. Specifically, the present solution belongs to the field of radiopharmaceuticals and relates to a compound represented by formula (IV) or a pharmaceutically acceptable salt thereof.

Abstract: A method includes: receiving the semiconductor device, wherein the semiconductor device includes: a well region; a doped region; a plurality of gate electrodes; a plurality of source regions; and a plurality of drain regions, wherein the plurality of gate electrodes, the plurality of source region and the plurality of drain regions form a plurality of transistors; and a bulk region disposed in the doped region. A first distance measured between a first transistor of the plurality of transistors and the bulk region is greater than a second distance measured between a second transistor of the plurality of transistors and the bulk region. The method further includes: applying a first voltage to the plurality of drain regions, wherein a first avalanche current generated around the first transistor and shunted through the bulk region is greater than a second avalanche current generated around the second transistor and shunted through the bulk region.

Abstract: A securing clip includes: an enclosure body including a first end, a second end, and one or more sidewalls that extend between the first end and the second end; one or more fragment module securing tangs extending, from one or more of the sidewalls, into the cavity such that when at least a portion of the fragment module is placed within the cavity, at least a portion of the fragment module securing tang is designed to engage with the fragment module and prevents and/or impedes removal of at least a portion of the fragment module from the cavity; and one or more substrate securing tangs extending from the enclosure body and away from the cavity, each substrate securing tang designed to prevent and/or impede removal of the securing clip when the securing clip is placed into a substrate aperture defined within the substrate

Abstract: An electronic paper display, comprising a carrier device, a memory, a display panel, a sensing device and a processing device. The carrier device is arranged on a logistics box. The memory is arranged on the carrier device, and is configured to store a logistics data. The display panel is arranged on the carrier device, and is configured to generate a control voltage according to the logistics data to adjust a plurality of positions of a plurality of electrophoretic particles. The sensing device comprises at least one sensor, and is configured to sense at least one state parameter of the logistics box to generate at least one sensing signal. The processing device is coupled to the memory, the display panel and the sensing device, and is configured to send the at least one sensing signal through wireless transmission technology.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer over a base substrate and an active layer over the channel layer. A source and a drain are over the active layer. A gate is over the active layer and laterally between the source and the drain. A dielectric is over the active layer and laterally surrounds the source, the drain, and the gate. A cap structure laterally contacts the source and is disposed laterally between the gate and the source. The source vertically extends to a top of the cap structure.

Abstract: A method and an electronic device are used to estimate osteoporosis. The method includes the following steps. An X-ray image is obtained. The X-ray image is input into a first convolutional neural network model to generate a bone probability heatmap of the X-ray image. A bone density estimation value is estimated based on the bone probability heatmap, the X-ray image, and a second convolutional neural network model.

Abstract: A method for preparing a hole transport layer of a perovskite solar cell, comprises S11, providing a conductive substrate; and S12: doping silver, gallium, selenium and sulfur with each other on the conductive substrate to obtain a hole transport layer. The present disclosure further provides a hole transport layer of a perovskite solar cell and a perovskite solar cell.

Abstract: In some embodiments, the present disclosure relates to a method of forming a high electron mobility transistor (HEMT) device. The method includes forming a passivation layer over a substrate. A source contact and a drain contact are formed within the passivation layer. A part of the passivation layer is removed to form a cavity. The cavity has a lower portion formed by a first sidewall and a second sidewall of the passivation layer and an upper portion formed by the first sidewall of the passivation layer and a sidewall of the source contact. A gate structure is formed within the passivation layer between the drain contact and the cavity. A cap structure is formed within the cavity.

Abstract: A humanized anti-neurotensin receptor 1 (NTSR1) antibody or an antigen-binding fragment thereof. Also, a method for treating, prophylactic treating and/or preventing diseases and/or disorders caused by or related to NTSR1 activity and/or signaling, and a method or kit for detecting NTSR1 in a sample.

Abstract: In an embodiment, an apparatus includes: a susceptor including substrate pockets; a gas injector disposed over the susceptor, the gas injector having first process regions, the gas injector including a first gas mixing hub and first distribution valves connecting the first gas mixing hub to the first process regions; and a controller connected to the gas injector and the susceptor, the controller being configured to: connect a first precursor material and a carrier gas to the first gas mixing hub; mix the first precursor material and the carrier gas in the first gas mixing hub to produce a first precursor gas; rotate the susceptor to rotate a first substrate disposed in one of the substrate pockets; and while rotating the susceptor, control the first distribution valves to sequentially introduce the first precursor gas at each of the first process regions as the first substrate enters each first process region.

Abstract: Methods, systems, and devices for power management associated with memory and a controller are described. A memory system performs a power management operation that accounts for power usage by any combination of application specific integrated circuits (ASICs) and memory arrays. The power management operation includes multiple logical unit numbers (LUNs) assigned to a single ASIC, which increases a quantity of bits for communicating a power usage. An ASIC included in a memory system may utilize twice as many bits for communicating power usage information when compared to a NAND array. As part of the power management operation, an ASIC may transmit, to a controller, a first set of bits indicating a power usage of the ASIC, a first subset of the set of bits transmitted during a first instance of a token ring and a second subset of the set of bits transmitted during a second instance of the token ring.

Abstract: Methods, systems, and devices for power arbitration for systems of electronic components are described. A system may include a power source, a signaling conductor coupled with a voltage source, and a set of electronic components. One or more of the electronic components may include respective circuitry coupled with the power source and a respective switching component (e.g., a transistor) coupled with the signaling conductor. In some implementations, an electronic component of the set may be configured to determine an operation of its respective circuitry that is associated with a power consumption from the power source. Based on such a determination, the electronic component may switch its respective switching component in accordance with an identifier associated with the electronic component, and determine whether to perform the operation based on monitoring a signal level of the signaling conductor during the switching.

Abstract: A dark area repair method and a dark area repair device of a curved liquid crystal display panel are provided. It is concluded through a summary that, under different curvatures, there is a quantitative relationship between a dark area and a first pretilt angle and a second pretilt angle. It determines whether a difference value of the first pretilt angle and the second pretilt angle is greater than or equal to a dark area critical value, and if so, there is no dark area. It is convenient to determine whether the dark area will show in the panel in advance in an early experimental stage, which can be used to guide an improvement of the dark area.

Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array. The control logic allocates power to one or more prioritized processing threads, of a plurality of processing threads that access the memory array, based on a value of a priority ring counter. The control logic starts a timer in response to detecting allocation of the power to a non-prioritized processing thread of the plurality of processing threads. While the timer is running, the control logic increments the priority ring counter before each power management cycle and prioritizes allocation of the power to the one or more prioritized processing threads located within a subset of the plurality of processing threads corresponding to a value of the priority ring counter.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first doped region in a substrate and comprising a first doping type. A gate structure is over the first doped region. A pair of contact regions are in the substrate on opposing sides of the gate structure and comprising the first doping type. The first doped region continuously laterally extends between the pair of contact regions and contacts the pair of contact regions. A second doped region is in the substrate and along a bottom of the first doped region. The second doped region comprises a second doping type opposite the first doping type.

Abstract: In some embodiments, an apparatus includes a memory and a processor. The processor is configured to receive an index file that associates a characteristic in a set of documents with a set of information associated with the characteristic in the set of documents. The processor is further configured to generate an index identifier associated with the index file and calculate a set of pseudorandom logical block identifiers associated with a set of storage locations of a database based on the index identifier. The processor is then configured to parse the index file into a set of index data portions and send a signal to the database to write each index data portion from the set of index data portions at a different storage location within the database as indicated by a different identifier from the set of pseudorandom logical block identifiers.

Abstract: Control logic on a memory die of a multi-die memory sub-system receives, from a memory sub-system controller, a data burst command indicating an upcoming data burst event and determines an expected current utilization in the memory sub-system during the data burst event. The control logic further determines whether the expected current utilization in the memory sub-system during the data burst event satisfies a threshold criterion and responsive to determining that the expected current utilization in the memory sub-system during the data burst event does not satisfy the threshold criterion, pauses one or more operations being executed by the control logic on the memory die until the expected current utilization in the memory sub-system during the data burst event satisfies the threshold criterion.

Abstract: A method includes selecting a particular ready/busy pin (R/B#) among a plurality of R/B# pins that are associated with respective memory dice among a plurality of memory dice of a memory device. The method further includes receiving, by at least one memory dice among the plurality of memory dice, signaling indicative of performance of a memory access while the particular R/B# pin is set to low, and, initiating an internal clocking signal subsequent to receipt of the signaling indicative of performance of the memory access, wherein the internal clocking signal is associated with timing of operations performed by the plurality of memory dice.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection circuit, coupled between a first reference terminal and a second reference terminal; the ESD protection circuit includes a first voltage divider, a second voltage divider, a first trigger circuit, a second trigger circuit, a first discharge component and a second discharge component. The first trigger circuit includes a first GaN based transistor, including a first source/drain and a second source/drain coupled to the first reference terminal and a gate coupled to the second reference terminal via the first voltage divider. The second trigger circuit includes a terminal coupled to the first reference terminal via the second voltage divider. The first discharge component includes a gate coupled between the first trigger circuit and the first voltage divider. The second discharge component includes a gate coupled between the second trigger circuit and the second voltage divider.

Abstract: A memory device might include registers configured to store expected peak current magnitudes corresponding to a plurality of memory devices containing the memory device, and a controller configured to cause the memory device to determine whether to initiate a next phase of an access operation in response to at least a first sum of an expected peak current magnitude for the next phase of the access operation in a selected operating mode and the expected peak current magnitudes of each of the registers other than a respective register of the memory device relative to a first current demand budget, and a second sum of the expected peak current magnitude for the next phase of the access operation in the selected operating mode and the expected peak current magnitudes of each of the registers other than a respective register of the memory device relative to a second, lower, current demand budget.