Abstract: A material feeding device includes a material barrel, a piston and an elastic member. The material barrel includes an opening; the piston matches with an inner wall of the material barrel through the opening, the piston encloses and forms a containing cavity for accommodating materials with the material barrel, and the piston is configured to be able to move along the inner wall of the material barrel. The elastic member is disposed between the inner wall of the material barrel and the piston, and adapted to connect the piston and the material barrel in a sealing manner.

Abstract: A humanized anti-neurotensin receptor 1 (NTSR1) antibody or an antigen-binding fragment thereof. Also, a method for treating, prophylactic treating and/or preventing diseases and/or disorders caused by or related to NTSR1 activity and/or signaling, and a method or kit for detecting NTSR1 in a sample.

Abstract: A memory device includes a set of memory dies, each memory die of the set of memory dies including a memory array and first control logic operatively coupled to the memory array, and an application-specific integrated circuit (ASIC) including a general-purpose input/output component (GPIO) including at least one digital pad communicably coupled to each memory die of the set of memory dies, and second control logic, operatively coupled to memory, to perform operations related to peak power management (PPM).

Abstract: A method for forming semiconductor devices includes providing a substrate with a conductive pad formed thereon; forming a transparent structure over the substrate, wherein the transparent structure includes a plurality of collimating pillars adjacent to the conductive pad; forming a light-shielding structure over the plurality of collimating pillars and the conductive pad; performing a cutting process to remove one or more materials directly above the conductive pad, while leaving remaining material to cover the conductive pad, wherein the material includes a portion of the light-shielding structure; and performing an etching process to remove the remaining material to expose the conductive pad.

Abstract: The present invention provides high affinity anti-CD40 monoclonal antibodies and related compositions, which may be used in any of a variety of therapeutic methods for the treatment of cancer and other diseases.

Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies including a memory array and control logic, operatively coupled with the memory array, to perform operations including identifying a data path operation with respect to the memory die. The memory die is associated with a channel. The operations further include determining, based on at least one value derived from a current budget ready status and a cache ready status, whether the channel is ready for the memory die to handle the data path operation, and in response to determining that the channel is ready for the memory die to handle the data path operation, causing the data path operation to be handled by the memory die.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a varactor comprising a reduced surface field (RESURF) region. The method includes forming a drift region having a first doping type within a substrate. A RESURF region having a second doping type is formed within the substrate such that the RESURF region is below the drift region. A gate structure is formed on the substrate. A pair of contact regions is formed within the substrate on opposing sides of the gate structure. The contact regions respectively abut the drift region and have the first doping type, and wherein the first doping type is opposite the second doping type.

Abstract: A memory device includes memory dice, each memory die including: a memory array; a memory to store a data structure; and control logic that includes: multiple processing threads to execute memory access operations on the memory array concurrently; a priority ring counter, the data structure to store an association between a value of the priority ring counter and a subset of the multiple processing threads; a threads manager to increment the value of the priority ring counter before a power management cycle and to identify one or more prioritized processing threads corresponding to the subset of the multiple processing threads; and a peak power manager coupled with the threads manager and to prioritize allocation of power to the one or more prioritized processing threads during the power management cycle.

Abstract: A memory device includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a memory die and control logic, operatively coupled with the memory die, to perform operations including receiving, during a current auxiliary data communication cycle, a token to enable auxiliary data communication, in response to receiving the token, determining whether to communicate auxiliary data via an auxiliary data channel to at least one other memory die of a plurality of memory dies, and in response to determining to communicate the auxiliary data via the auxiliary data channel to the at least one other memory die, causing the auxiliary data to be communicated to the at least one other memory die.

Abstract: A display device includes a panel, a conductive layer, a first color filter array and a second color filter array. The panel has a display surface and multiple sub-pixel regions where the multiple sub-pixel regions and the conductive layer are on this display surface. The first color filter array including multiple first color filter elements is disposed on the conductive layer while the second color filter array including multiple second color filter elements is disposed on the first color filter array. One first overlaid region and one second overlaid region are defined by the orthogonal projections of the color filter elements within one of the sub-pixel regions. In one sub-pixel region, a section of the first overlaid region does not overlap a section of the second overlaid region.

Abstract: The present disclosure provides a electrostatic discharge (ESD) protection circuit, coupled between a first reference terminal and a second reference terminal; the ESD protection circuit includes a first voltage divider, a second voltage divider, a first trigger circuit and a second trigger circuit. The first trigger circuit includes a first terminal and a second terminal, wherein the first terminal is coupled to the first reference terminal, and the second terminal is coupled to the second reference terminal via the first voltage divider. The second trigger circuit includes a first terminal and a second terminal, wherein the first terminal is coupled to the second reference terminal, the second terminal is coupled to the first reference terminal via the second voltage divider, and the second trigger circuit and the first trigger circuit are in parallel connection.

Abstract: The present application discloses a liquid crystal display panel, a method for manufacturing the liquid crystal display panel, and a curved display. The liquid crystal display panel is configured with an alignment layer only on an array substrate, but not on an opposing substrate opposite to the array substrate. After photo-alignment, a pretilt angle of liquid crystal molecules near the array substrate is greater than a pretilt angle of liquid crystal molecules near the opposing substrate to effectively mitigate a problem of “black clusters.

Abstract: A method includes selecting a particular ready/busy pin (R/B #) among a plurality of R/B # pins that are associated with respective memory dice among a plurality of memory dice of a memory device. The method further includes receiving, by at least one memory dice among the plurality of memory dice, signaling indicative of performance of a memory access while the particular R/B # pin is set to low, and, initiating an internal clocking signal subsequent to receipt of the signaling indicative of performance of the memory access, wherein the internal clocking signal is associated with timing of operations performed by the plurality of memory dice.

Abstract: A memory device might include a controller configured to cause the memory device to generate a first sum of expected peak current magnitudes for a plurality of memory devices, and generate a second sum of expected peak current magnitudes for a subset of the plurality of memory devices, if the memory device were to initiate a next phase of an access operation in a selected operating mode; to compare the first sum to a first current demand budget for the plurality of the memory devices; to compare the second sum to a second current demand budget for the subset of memory devices; and to initiate the next phase of the access operation in the selected operating mode in response to the first sum being less than or equal to the first current demand budget and the second sum being less than or equal to the second current demand budget.

Abstract: A variety of applications can include a memory device having a memory die designed to control a power budget for a cache and a memory array of the memory die. A first flag received from a data path identifies a start of a cache operation on the data and a second flag from the data path identifies an end of the cache operation. A controller for peak power management can be implemented to control the power budget based on determination of usage of current associated with the cache from the first and second flags. In various embodiments, the controller can be operable to feedback a signal to a memory controller external to the memory die to adjust an operating speed of an interface from the memory controller to the memory die. Additional devices, systems, and methods are discussed.

Abstract: A method includes receiving a request to perform a memory access operation, wherein the memory access operation includes a set of sub-operations, selecting a current quantization data structure from a plurality of current quantization data structures, wherein each current quantization data structure of the plurality of current quantization data structures maintains, for each sub-operation of the set of sub-operations, a respective current quantization value reflecting an amount of current that is consumed by the respective sub-operation based on a set of peak power management (PPM) operation parameters, and causing the memory access operation to be performed using PPM based on the current quantization data structure.

Abstract: A memory device includes memory dies. Each memory die includes a memory array and control logic, operatively coupled with the memory array, to perform operations for implementing peak power management (PPM) data burst communication. The operations include monitoring a data burst with respect to the memory array, detecting a current reservation trigger associated with the data burst, in response detecting the current reservation trigger, reserving an initial amount of current reflecting a maximum current consumption value associated with a maximum data transfer speed of the data burst, detecting a plurality of input/output cycles of the data burst following the preamble period, and in response to detecting the number of input/output cycles, reserving, based on an analysis of the plurality of input/output cycles, a subsequent amount of current reflecting an actual current consumption value associated with an actual data transfer speed of the data burst.

Abstract: A pipe coupling assembly for joining two sections of polymer pipe, the pipe coupling assembly comprising: an insert configured for positioning within an end region of a first section of polymer pipe and an end region of a second section of polymer pipe, such that an annular gap is formed between the insert and the end regions of polymer pipe; an adhesive configured for sealing the annular gap between the insert and the end regions; and an external coupler for positioning over the end regions and joining the first and second sections of polymer pipe.

Abstract: Memory device might include a controller configured to cause the memory device to determine whether the memory device is waiting to initiate a next phase of an access operation, and in response to determining that the memory device is waiting to initiate the next phase, determine whether there is sufficient available current budget to initiate the next phase in a selected operating mode in response to at least the priority token of the memory device, an expected peak current magnitude for the next phase in the selected operating mode, and additional expected peak current magnitudes for other memory devices. In response to determining that there is sufficient available current budget to initiate the next phase in the selected operating mode, the memory device might output the expected peak current magnitude for the next phase in the selected operating mode from the memory device.

Abstract: A dark area repair method and a dark area repair device of a curved liquid crystal display panel are provided. It is concluded through a summary that, under different curvatures, there is a quantitative relationship between a dark area and a first pretilt angle and a second pretilt angle. It determines whether a difference value of the first pretilt angle and the second pretilt angle is greater than or equal to a dark area critical value, and if so, there is no dark area. It is convenient to determine whether the dark area will show in the panel in advance in an early experimental stage, which can be used to guide an improvement of the dark area.