Abstract: An image analyzation method and an image analyzation device are disclosed. The method includes: obtaining a first image which presents at least a first object and a second object; analyzing the first image to detect a first central point between a first endpoint of the first object and a second endpoint of the second object; determining a target region based on the first central point as a center of the target region; capturing a second image located in the target region from the first image; and analyzing the second image to generate status information which reflects a gap status between the first object and the second object.

Abstract: The present disclosure relates to a voltage regulating circuit, including an impedance circuit, a control unit and a power supply circuit. The impedance circuit has a first node and a second node, wherein the second node is electrically coupled to a load. The control unit is electrically coupled to the first node and configured to control a first voltage value of the first node according to a control signal. An input terminal of the power supply circuit is electrically coupled to the second node. An output of the power supply circuit is electrically coupled to the load. The power supply circuit is configured d to output a control voltage to the load according to a second voltage value of the second node.

Abstract: Memory device might include a controller configured to cause the memory device to determine whether the memory device is waiting to initiate a next phase of an access operation, and in response to determining that the memory device is waiting to initiate the next phase, determine whether there is sufficient available current budget to initiate the next phase in a selected operating mode in response to at least the priority token of the memory device, an expected peak current magnitude for the next phase in the selected operating mode, and additional expected peak current magnitudes for other memory devices. In response to determining that there is sufficient available current budget to initiate the next phase in the selected operating mode, the memory device might output the expected peak current magnitude for the next phase in the selected operating mode from the memory device.

Abstract: A method includes forming a body region of a first conductivity type and a doped region of a second conductivity type in a semiconductor substrate; forming a gate structure the substrate, and first gate spacers respectively on first and second sides of the gate structure; depositing a second spacer layer and a third spacer layer over the gate structure; patterning the third spacer layer into third gate spacers respectively on the first and second sides of the gate structure; removing a first one of the third gate spacers from the first side of the gate structure, while leaving a second one of the third gate spacers on the second side of the gate structure; and patterning the second spacer layer into a second gate spacer by using the second one of the third gate spacers as an etching mask.

Abstract: A color filter module is provided. The color filter module is arranged on a display panel. The color filter module includes a transparent substrate and a color resist layer. The transparent substrate includes multiple sub-pixel regions arranged in an array. The color resist layer is arranged on the transparent substrate. The color resist layer includes multiple color resist units. The color resist units are respectively arranged across at least two sub-pixel regions, and the color resist units form a staggered array on the transparent substrate.

Abstract: A color filter module is provided. The color filter module is disposed on an electrophoretic display panel. The color filter module includes a transparent substrate and a color resist layer. The transparent substrate includes a plurality of pixel regions arranged in an array. Each of the plurality of pixel regions includes a plurality of sub-pixel regions. The color resist layer is disposed on the transparent substrate. Among the plurality of sub-pixel regions of the transparent substrate, a first sub-pixel region and a second sub-pixel region that correspond to a same color and are adjacent to each other are provided with a plurality of color resist units of the same color of the color resist layer. The plurality of color resist units are arranged in an array and arranged in a discontinuous pattern.

Abstract: A single-beam three-degree-of-freedom homodyne laser interferometer based on an array detector. A single-frequency laser beam is input to a Michelson interference structure, the measurement beam and the reference beam perform non-coaxial interference and form a single-beam homodyne interference signal by setting the angle of a reference plane mirror, the array detector is selected to effectively receive the single-beam homodyne interference signal, and finally, three-degree-of-freedom signal linear decoupling on the single-beam homodyne interference signal is achieved through a three-degree-of-freedom decoupling method based on Lissajous ellipse fitting.

Abstract: An avalanche-protected field effect transistor includes, within a semiconductor substrate, a body semiconductor layer and a doped body contact region having a doping of a first conductivity type, and a source region a drain region having a doping of a second conductivity type. A buried first-conductivity-type well may be located within the semiconductor substrate. The buried first-conductivity-type well underlies, and has an areal overlap in a plan view with, the drain region, and is vertically spaced apart from the drain region, and has a higher atomic concentration of dopants of the first conductivity type than the body semiconductor layer. The configuration of the field effect transistor induces more than 90% of impact ionization electrical charges during avalanche breakdown to flow from the source region, to pass through the buried first-conductivity-type well, and to impinge on a bottom surface of the drain region.

Abstract: Provided are a latch mechanism and an electronic device case. The latch mechanism includes a base assembly, a pressing assembly and a first elastic member. The base assembly has an accommodating cavity, and a wall surface of the base assembly has a first through hole and a second through hole which are respectively communicated with the accommodating cavity. The pressing assembly includes a main body part, a button part and a bolt part, the main body part is disposed in the accommodating cavity, and the button part and the bolt part are respectively disposed on the main body part. The first elastic member is located in the accommodating cavity, one end of the first elastic member abuts against an inner wall of the accommodating cavity and the other end abuts against the main body part.

Abstract: A request is received from a host system to execute a portion of a memory management operation associated with a memory cell of a plurality of memory cells of one or more memory devices. A voltage parameter level associated with execution of the portion of the memory management operation is identified. A determination is made that a comparison of the voltage parameter level with a voltage parameter level threshold satisfies a condition. A power management action is performed in response to the condition being satisfied.

Abstract: A liquid cooling device includes a liquid cooling conductor, a detecting probe, and a determining circuit. The liquid cooling conductor includes a chamber defined therein for communicating with the outside, the chamber is configured to accommodate the coolant, and the surface of the liquid cooling conductor is provided with at least one communicating port communicating with the chamber; wherein the liquid cooling conductor is formed joining at least two combination blocks, and at least one of the two combination blocks is a metal conductor. The detecting probe is disposed on the liquid cooling conductor and normally electrically disconnected from the metal conductor. The determining circuit is electrically connected to the metal conductor and the detecting probe, and generates a liquid leakage alarm signal when the metal conductor and the detecting probe are electrically connected.

Abstract: A semiconductor device includes a gate structure, a double diffused region, a source region, a drain region, a first gate spacer, and a second gate spacer. The gate structure is over a semiconductor substrate. The double diffused region is in the semiconductor substrate and laterally extends past a first side of gate structure. The source region is in the semiconductor substrate and is adjacent a second side of the gate structure opposite the first side. The drain region is in the double diffused region in the semiconductor substrate and is of a same conductivity type as the double diffused region. The first gate spacer is on the first side of the gate structure. The second gate spacer extends upwardly from the double diffused region along an outermost sidewall of the first gate spacer and terminates prior to reaching a top surface of the gate structure.

Abstract: A memory device includes a first memory die of a plurality of memory dies, the first memory die comprising a first memory array and a first power management component, wherein the first power management component is configured to send a first test value to one or more other power management components on one or more other memory dies of the plurality of memory dies during a first power management cycle of a first power management token loop.

Abstract: In some embodiments, an apparatus includes a memory and a processor. The processor is configured to receive an index file that associates a characteristic in a set of documents with a set of information associated with the characteristic in the set of documents. The processor is further configured to generate an index identifier associated with the index file and calculate a set of pseudorandom logical block identifiers associated with a set of storage locations of a database based on the index identifier. The processor is then configured to parse the index file into a set of index data portions and send a signal to the database to write each index data portion from the set of index data portions at a different storage location within the database as indicated by a different identifier from the set of pseudorandom logical block identifiers.

Abstract: A fan assembly including a base, a fan, a light-emitting unit, and a lighting effect component is provided. The fan is rotatably disposed above the base, and includes a central part and multiple blades extending outwards from the central part, and each of the blades has a top surface away from the base. The light-emitting unit is disposed on the base and located between the base and the central part of the fan. The lighting effect component is disposed on the base and surrounds the light-emitting unit. A projection of the lighting effect component projected onto the base is greater than a projection of the fan projected onto the base. A height of the lighting effect component protruding from the base is less than a distance between the top surface of one of the blades and the base. The lighting effect component includes an inclined inner surface.

Abstract: A wireless power supply apparatus including a signal transmitting terminal and a signal receiving terminal is provided. The signal transmitting terminal encodes a digital data into a control signal and transmits a power supply signal in a manner of wireless communication according to the control signal. The signal receiving terminal receives the power supply signal from the signal transmitting terminal in the manner of wireless communication. The signal receiving terminal converts the power supply signal into a power source signal and a data signal and decodes the data signal into the digital data.

Abstract: A color filter array includes a first color resist, a second color resist, and a third color resist. The first color resist has a first color, the second color resist has a second color, and the third color resist has a third color. A transparency of the third color resist is greater than transparencies of the first color resist and the second color resist. The first color resist has a first edge and a second edge arranged along a first direction. The second color resist has a first edge and a second edge arranged along a first direction. The first color resist and the second color resist are arranged along a second direction. The first edge of the first color resist, the second edge of the second color resist, and the second edge of the first color resist are arranged sequentially along the first direction.

Abstract: A supporter is provided, and includes a base, a holder, and a linkage assembly. The base has a surface and a groove that is formed on the surface. The holder is disposed on the surface of the base. The linkage assembly is disposed in the base. The linkage assembly is rotatable relative to the base. The linkage assembly includes a first shaft, a second shaft, and a linkage member. The first shaft is at least partially disposed in the groove. The second shaft is connected to the holder. The linkage member is connected to the first shaft and the second shaft. The linkage member is configured to link the first shaft to the second shaft.

Abstract: A variety of applications can include a memory device having a memory die designed to control a power budget for a cache and a memory array of the memory die. A first flag received from a data path identifies a start of a cache operation on the data and a second flag from the data path identifies an end of the cache operation. A controller for peak power management can be implemented to control the power budget based on determination of usage of current associated with the cache from the first and second flags. In various embodiments, the controller can be operable to feedback a signal to a memory controller external to the memory die to adjust an operating speed of an interface from the memory controller to the memory die. Additional devices, systems, and methods are discussed.

Abstract: A variety of applications can include multiple memory die packages configured to engage in peak power management (PPM) across the multiple packages of memory dies. A communication line coupled to each memory die in the multiple memory die packages can be used to facilitate the PPM. A global management die can start a communication sequence among the multiple memory die packages to share a current budget across the multiple memory die packages by driving a signal on the communication line. Local management dies can use the received signal having clock pulses driven by the global management die on the communication line to engage in the PPM. To engage in global PPM, each memory die can be structured, to be selected as the global management die or a local management die, with one or more controllers to interface with the multiple memory die packages and to handle current budget limits.