Patents by Inventor Liang Yu

Liang Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • 3D ARCHITECTURE OF TERNARY CONTENT-ADDRESSABLE MEMORY METHOD FOR THE SAME
    Publication number: 20220028858
    Abstract: Disclosed is a 3D architecture of ternary content-addressable memory (TCAM), comprising a first transistor layer, a second transistor layer, a third transistor layer and a fourth transistor layer. The first transistor layer and the second transistor layer are disposed on a first plane. The third transistor layer and the fourth transistor layer are respectively stacked on the first transistor layer and the second transistor layer in a second direction perpendicular to the first plane. Two of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are a first transistor and a second transistor of a first memory cell of the TCAM. The other two of the first transistor layer, the second transistor layer, the third transistor layer and the fourth transistor layer are a first transistor and a second transistor of a second memory cell of the TCAM.
    Type: Application
    Filed: July 23, 2020
    Publication date: January 27, 2022
    Inventor: Liang-Yu CHEN
  • SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME
    Publication number: 20220029035
    Abstract: A method for forming semiconductor devices includes providing a substrate with a conductive pad formed thereon; forming a transparent structure over the substrate, wherein the transparent structure includes a plurality of collimating pillars adjacent to the conductive pad; forming a light-shielding structure over the plurality of collimating pillars and the conductive pad; performing a cutting process to remove one or more materials directly above the conductive pad, while leaving remaining material to cover the conductive pad, wherein the material includes a portion of the light-shielding structure; and performing an etching process to remove the remaining material to expose the conductive pad.
    Type: Application
    Filed: October 8, 2021
    Publication date: January 27, 2022
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Hui LEE, Han-Liang TSENG, Jiunn-Liang YU, Kwang-Ming LIN, Yin CHEN, Si-Twan CHEN, Hsueh-Jung LIN, Wen-Chih LU, Chih-Hsien CHEN
  • Vehicle control method and vehicle control system
    Patent number: 11225285
    Abstract: A vehicle control method and a vehicle control system are provided. A lateral distance between a vehicle and a tunnel wall of a tunnel is obtained through a lidar sensor when the vehicle is moving in a lane in the tunnel. A lateral offset parameter between the vehicle and a lane centerline is obtained based on the lateral distance. A moving direction of the vehicle is controlled according to the lateral offset parameter.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: January 18, 2022
    Assignee: Acer Incorporated
    Inventor: Liang-Yu Ke
  • Management of peak current of memory dies in a memory sub-system
    Patent number: 11216219
    Abstract: A memory management operation is executed on a plurality of memory dies of a memory sub-system. The memory sub-system determines whether a first measured current level corresponding to execution of the memory management operation satisfies a condition pertaining to a threshold peak current level. The memory sub-system determines whether a second measured current level corresponding to execution of the memory management operation satisfies the condition pertaining to the threshold peak current level. Mask data is generated identifying the first measured current level and the second measured current level. A request is received from a host system to execute the memory management operation. The memory sub-system performs, based on the mask data, a peak current management action during execution of the memory management operation.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Liang Yu, John Paul Aglubat, Fulvio Rori
  • Management of power during memory device reset and initialization
    Patent number: 11200001
    Abstract: A system to send a first command to a first memory die of a plurality of memory dies of a memory sub-system the first command to execute an initialization process. The system reads a first bit value from the first memory die, the first bit value indicating the first memory die is executing a peak current phase of the initialization process. The system reads a second bit value from the first memory die, the second bit value indicating the first memory die is executing a safe phase of the initialization process. In response to reading the second bit value, a second command is sent to a second memory die to execute the initialization process.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Liang Yu, Jonathan Parry
  • Cap structure coupled to source to reduce saturation current in HEMT device
    Patent number: 11195945
    Abstract: In some embodiments, the present disclosure relates to a high voltage device that includes a substrate comprising a first semiconductor material. A channel layer that comprises a second semiconductor material is arranged over the substrate. An active layer that comprises a third semiconductor material is arranged over the channel layer. Over the active layer is a source contact spaced apart from a drain contact. A gate structure is arranged laterally between the source and drain contacts and over the active layer to define a high electron mobility transistor (HEMT) device. Between the gate structure and the source contact is a cap structure, which is coupled to the source contact and laterally spaced from the gate structure. The cap structure and a gate electrode of the gate structure comprise a same material.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: December 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Cheng Lin, Chen-Bau Wu, Chun Lin Tsai, Haw-Yun Wu, Liang-Yu Su, Yun-Hsiang Wang
  • MANAGEMENT OF POWER DURING MEMORY DEVICE RESET AND INITIALIZATION
    Publication number: 20210357149
    Abstract: A system to send a first command to a first memory die of a plurality of memory dies of a memory sub-system the first command to execute an initialization process. The system reads a first bit value from the first memory die, the first bit value indicating the first memory die is executing a peak current phase of the initialization process. The system reads a second bit value from the first memory die, the second bit value indicating the first memory die is executing a safe phase of the initialization process. In response to reading the second bit value, a second command is sent to a second memory die to execute the initialization process.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 18, 2021
    Inventors: Liang Yu, Jonathan Parry
  • NEGATIVE PRESSURE PROTECTION SYSTEM
    Publication number: 20210353484
    Abstract: A negative pressure protection system has a cover enclosing an inner space, a ventilation duct fluidly communicating with an air outlet port of the cover, a filter having an inlet end communicating with the ventilation duct, and an air exhausting device connected to an outlet end of the filter. The air exhausting device draws air out from the inner space of the cover via the ventilation duct. The air is filtered and purified by the filter and then is exhausted away by the exhausting device.
    Type: Application
    Filed: December 3, 2020
    Publication date: November 18, 2021
    Applicant: GrowTrend Biomedical Co., Ltd.
    Inventors: Ching-Liang YU, Pei-Yin OU, Yun-Yueh LIU, Neng Yu PAN
  • Power control device, computer system, and power control method thereof
    Patent number: 11175720
    Abstract: A power control device for a computer system includes a detecting module, configured to detect an open/close state of a display device to generate an open/close signal; and a controller, coupled to the detecting module and coupled to a power supply device through a system management bus, configured to generate an enabling signal to conduct or block a power source of the computer system provided by the power supply device, and to wake up the power supply device, which is in a power saving mode, according to the open/close signal.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: November 16, 2021
    Assignee: Wistron Corporation
    Inventors: Liang-Yu Lai, Meng-Che Lian, Yun-Lin Tsai, Chun-Lung Hsiao
  • Semiconductor devices and methods for forming the same
    Patent number: 11177397
    Abstract: A method for forming semiconductor devices includes providing a substrate with a conductive pad formed thereon; forming a transparent structure over the substrate, wherein the transparent structure includes a plurality of collimating pillars adjacent to the conductive pad; forming a light-shielding structure over the plurality of collimating pillars and the conductive pad; performing a cutting process to remove one or more materials directly above the conductive pad, while leaving remaining material to cover the conductive pad, wherein the material includes a portion of the light-shielding structure; and performing an etching process to remove the remaining material to expose the conductive pad.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: November 16, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Hui Lee, Han-Liang Tseng, Jiunn-Liang Yu, Kwang-Ming Lin, Yin Chen, Si-Twan Chen, Hsueh-Jung Lin, Wen-Chih Lu, Chih-Hsien Chen
  • MANAGEMENT OF PEAK CURRENT OF MEMORY DIES IN A MEMORY SUB-SYSTEM
    Publication number: 20210349663
    Abstract: A memory management operation is executed on a plurality of memory dies of a memory sub-system. The memory sub-system determines whether a first measured current level corresponding to execution of the memory management operation satisfies a condition pertaining to a threshold peak current level. The memory sub-system determines whether a second measured current level corresponding to execution of the memory management operation satisfies the condition pertaining to the threshold peak current level. Mask data is generated identifying the first measured current level and the second measured current level. A request is received from a host system to execute the memory management operation. The memory sub-system performs, based on the mask data, a peak current management action during execution of the memory management operation.
    Type: Application
    Filed: May 11, 2020
    Publication date: November 11, 2021
    Inventors: Liang Yu, John Paul Aglubat, Fulvio Rori
  • Open-drain transistor monitoring circuit in a multi-chip package to control power
    Patent number: 11164784
    Abstract: A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides, for each respective signal, driving a respective open-drain transistor to conduct, in which an output of each open-drain transistor connects to the common node and the common node connects to a reference voltage, to change a voltage of a common node corresponding to the respective signal; and utilizing the voltage of the common node to indicate total power consumption of the dice.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: November 2, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Jonathan S. Parry, Stephen L. Miller, Liang Yu
  • POWER MANAGEMENT BASED ON DETECTED VOLTAGE PARAMETER LEVELS IN A MEMORY SUB-SYSTEM
    Publication number: 20210334020
    Abstract: A set of memory management operations is executed on multiple memory dies of a memory sub-system. Voltage parameter levels corresponding to the set of memory management operations are determined. Information representing a voltage parameter level and a corresponding portion of the set of memory management operations is determined based on the set of voltage parameter levels. A request is received from a host system to execute a target portion of a memory management operation. First information corresponding to the target portion of the memory management operation is identified. Based on the first voltage parameter level, power management action is performed.
    Type: Application
    Filed: April 22, 2020
    Publication date: October 28, 2021
    Inventors: Liang Yu, William C. Filipiak
  • SETTING A POWER MODE BASED ON A WORKLOAD LEVEL IN A MEMORY SUB-SYSTEM
    Publication number: 20210294407
    Abstract: A workload level in an incoming request queue is determined based on one or more operations requested by a host system for execution by a memory sub-system. Based on the workload level in the incoming request queue, a set of memory dies of the memory sub-system to be activated for execution of the one or more operations is identified. Based on a power budget level, a power mode configuration for a memory die of the set of memory dies is determined. One or more parameters of the memory die are configured to establish the power mode configuration.
    Type: Application
    Filed: March 17, 2020
    Publication date: September 23, 2021
    Inventors: Liang Yu, Jonathan Parry
  • Recovery method for terminal device startup failure and terminal device
    Patent number: 11119844
    Abstract: Embodiments provide a recovery method for a terminal device startup failure and a terminal device. The method includes: determining that a failure indication event occurs in a startup process, where the failure indication event is used to indicate a startup failure; determining at least one recovery policy based on a type of the failure indication event and/or a cause of the failure indication event; and performing startup recovery based on the at least one recovery policy.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: September 14, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Liang Zhang, Dechun Qi, Xiaoyan Zhou, Zhiqiang Li, Liang Yu, Dengzhou Xia, Chunhua Hu, Zhongsheng Yan
  • REDUCED SURFACE FIELD LAYER IN VARACTOR
    Publication number: 20210273119
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a varactor comprising a reduced surface field (RESURF) region. The method includes forming a drift region having a first doping type within a substrate. A RESURF region having a second doping type is formed within the substrate such that the RESURF region is below the drift region. A gate structure is formed on the substrate. A pair of contact regions is formed within the substrate on opposing sides of the gate structure. The contact regions respectively abut the drift region and have the first doping type, and wherein the first doping type is opposite the second doping type.
    Type: Application
    Filed: May 19, 2021
    Publication date: September 2, 2021
    Inventors: Liang-Yu Su, Chih-Wen Yao, Hsiao-Chin Tuan, Ming-Ta Lei
  • ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND SEMICONDUCTOR CIRCUIT
    Publication number: 20210249404
    Abstract: The present disclosure provides a electrostatic discharge (ESD) protection circuit, coupled between a first reference terminal and a second reference terminal; the ESD protection circuit includes a first voltage divider, a second voltage divider, a first trigger circuit and a second trigger circuit. The first trigger circuit includes a first terminal and a second terminal, wherein the first terminal is coupled to the first reference terminal, and the second terminal is coupled to the second reference terminal via the first voltage divider. The second trigger circuit includes a first terminal and a second terminal, wherein the first terminal is coupled to the second reference terminal, the second terminal is coupled to the first reference terminal via the second voltage divider, and the second trigger circuit and the first trigger circuit are in parallel connection.
    Type: Application
    Filed: March 31, 2021
    Publication date: August 12, 2021
    Inventors: MING-FANG LAI, LIANG-YU SU, HANG FAN
  • SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME
    Publication number: 20210217906
    Abstract: A method for forming semiconductor devices includes providing a substrate with a conductive pad formed thereon; forming a transparent structure over the substrate, wherein the transparent structure includes a plurality of collimating pillars adjacent to the conductive pad; forming a light-shielding structure over the plurality of collimating pillars and the conductive pad; performing a cutting process to remove one or more materials directly above the conductive pad, while leaving remaining material to cover the conductive pad, wherein the material includes a portion of the light-shielding structure; and performing an etching process to remove the remaining material to expose the conductive pad.
    Type: Application
    Filed: January 9, 2020
    Publication date: July 15, 2021
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Hui LEE, Han-Liang TSENG, Jiunn-Liang YU, Kwang-Ming LIN, Yin CHEN, Si-Twan CHEN, Hsueh-Jung LIN, Wen-Chih LU, Chih-Hsien CHEN
  • Braking control method, braking system and vehicle
    Patent number: 11027734
    Abstract: A braking control method for a braking system of a vehicle is provided according to an exemplary embodiment of the disclosure. The braking control method comprises: obtaining a total braking distance and a first speed of the vehicle; obtaining braking delay information related to the braking system, wherein the braking delay information includes first time information and second time information, the first time information reflects a delay time of a braking signal, and the second time information reflects a preparation time for performing a braking operation according to the braking signal by the braking system; obtaining deceleration information according to the total braking distance, the first speed and the braking delay information; generating the braking signal according to the deceleration information; and performing the braking operation according to the braking signal.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: June 8, 2021
    Assignee: Acer Incorporated
    Inventors: Liang-Yu Ke, Yu-Min Cheng
  • Reduced surface field layer in varactor
    Patent number: 11018266
    Abstract: Various embodiments of the present disclosure are directed towards a varactor comprising a reduced surface field (RESURF) region. In some embodiments, the varactor includes a drift region, a gate structure, a pair of contact regions, and a RESURF region. The drift region is within a substrate and has a first doping type. The gate structure overlies the drift region. The contact regions are within the substrate and overlie the drift region. Further, the contact regions have the first doping type. The gate structure is laterally sandwiched between the contact regions. The RESURF region is in the substrate, below the drift region, and has a second doping type. The second doping type is opposite the first doping type. The RESURF region aids in depleting the drift region under the gate structure, which decreases the minimum capacitance of the varactor and increases the tuning range of the varactor.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Liang-Yu Su, Chih-Wen Yao, Hsiao-Chin Tuan, Ming-Ta Lei