Abstract: A set of memory management operations is executed on multiple memory dies of a memory sub-system. Voltage parameter levels corresponding to the set of memory management operations are determined. Information representing a voltage parameter level and a corresponding portion of the set of memory management operations is determined based on the set of voltage parameter levels. A request is received from a host system to execute a target portion of a memory management operation. First information corresponding to the target portion of the memory management operation is identified. Based on the first voltage parameter level, power management action is performed.

Abstract: A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides for converting each respective signal to a respective analog voltage to drive a common node; and utilizing a charge storage device coupled to the common node to accumulate the respective analog voltages from the dice, where the accumulated voltage indicates total power consumption of the dice.

Abstract: A method for viewing an application program, graphical user interface, and a terminal, where the method includes receiving a first input, where the first input viewing a plurality of running application programs stacked for displaying, obtaining an input position corresponding to the first input and non-position information corresponding to the first input in the input position, determining, according to the input position and the non-position information, an application program reachable by the first input in the input position, and displaying the application program reachable by the first input in the input position. Hence, the method for viewing the application program, the graphical user interface, and the terminal simplify a user's operation of viewing a blocked application program in the stacked application programs.

Abstract: An optical sensor includes pixels disposed in a substrate. A light collimating layer is disposed on the substrate and includes a transparent layer, a light-shielding layer, and transparent pillars. The transparent layer blanketly disposed on the substrate covers the pixels and the region between the pixels. The light-shielding layer is disposed on the transparent layer and between the transparent pillars. The transparent pillars penetrating through the light-shielding layer are correspondingly disposed on the pixels.

Abstract: A portion of a memory management operation associated with a first current level that satisfies a condition pertaining to a threshold current level and a second current level that satisfies the condition pertaining to the threshold current level is identified. Mask data associated with the portion of the memory management operation is identified. Based on the mask data, a current management action is performed during execution of a requested memory management operation received from a host system.

Abstract: A VGA card assembly includes a VGA card with a circuit board for generating a status signal and a monitoring device. The monitoring device has a microprocessor for receiving the status signal, a status display and a non-volatile memory with at least one first storage block and at least one second storage block. Before completely writing a second file into the second storage block, the microprocessor obtains a first file stored in the first storage block, and enables the status display to output an image according to at least one of the status signal and the first file. After completely writing the second file into the second storage block, the microprocessor obtains the second file stored in the second storage block, and enables the status display to output an image according to at least one of the status signal and the second file.

Abstract: A system to send a first command to execute an initialization process on a first memory die of a plurality of memory dies of a memory sub-system. The system reads a bit value indicating that the first memory die is executing a low peak current draw phase of the initialization process. In response to reading the bit value, sending a second command to a second memory die of the plurality of memory dies of the memory sub-system, the second command to execute the initialization process on the second memory die.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer disposed over a base substrate, and an active layer disposed on the channel layer. A source contact and a drain contact are over the active layer and are laterally spaced apart from one another along a first direction. A gate electrode is arranged on the active layer between the source contact and the drain contact. A passivation layer is arranged on the active layer and laterally surrounds the source contact, the drain contact, and the gate electrode. A conductive structure is electrically coupled to the source contact and is disposed laterally between the gate electrode and the source contact. The conductive structure extends along an upper surface and a sidewall of the passivation layer.

Abstract: A pipe coupling assembly for joining two sections of polymer pipe, the pipe coupling assembly comprising: an insert configured for positioning within an end region of a first section of polymer pipe and an end region of a second section of polymer pipe, such that an annular gap is formed between the insert and the end regions of polymer pipe; an adhesive configured for sealing the annular gap between the insert and the end regions; and an external coupler for positioning over the end regions and joining the first and second sections of polymer pipe.

Abstract: Provided are a latch mechanism and an electronic device case. The latch mechanism includes a base assembly, a pressing assembly and a first elastic member. The base assembly has an accommodating cavity, and a wall surface of the base assembly has a first through hole and a second through hole which are respectively communicated with the accommodating cavity. The pressing assembly includes a main body part, a button part and a bolt part, the main body part is disposed in the accommodating cavity, and the button part and the bolt part are respectively disposed on the main body part. The first elastic member is located in the accommodating cavity, one end of the first elastic member abuts against an inner wall of the accommodating cavity and the other end abuts against the main body part.

Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. Each of the memory cells is coupled to one of the first search lines and one of the second search lines. The current sensing units, coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units.

Abstract: Embodiments of this application provide a recovery method for a terminal device startup failure and a terminal device. The method includes: determining that a failure indication event occurs in a startup process, where the failure indication event is used to indicate a startup failure; determining at least one recovery policy based on a type of the failure indication event and/or a cause of the failure indication event; and performing startup recovery based on the at least one recovery policy.

Abstract: The present disclosure relates to a voltage regulating circuit, including an impedance circuit, a control unit and a power supply circuit. The impedance circuit has a first node and a second node, wherein the second node is electrically coupled to a load. The control unit is electrically coupled to the first node and configured to control a first voltage value of the first node according to a control signal. An input terminal of the power supply circuit is electrically coupled to the second node. An output of the power supply circuit is electrically coupled to the load. The power supply circuit is configured d to output a control voltage to the load according to a second voltage value of the second node.

Abstract: The present disclosure provides an adaptor, comprising an adapting bracket, an adapting member, and at least one locking component. The adapting bracket comprises a chute comprising two opposite sidewalls and a bottom wall. The bottom wall is disposed between the two sidewalls. The adapting member is disposed on the adapting bracket. The adapting member comprises an adapting interface and is in communicating with the chute. The at least one locking component is disposed in the adapting bracket. Each of the locking components comprises a locking member movably extending into the chute. When an electronic component is inserted in the chute, a mating interface of the electronic component is connected to the adapting interface, and the locking member is inserted into an engaging groove of the electronic component. By protecting the electronic component with the adapting bracket, it is possible to avoid damage to the electronic component from impacts.

Abstract: A semiconductor device includes a gate structure, a double diffused region, a source region, a drain region, a first gate spacer, and a second gate spacer. The gate structure is over a semiconductor substrate. The double diffused region is in the semiconductor substrate and laterally extends past a first side of gate structure. The source region is in the semiconductor substrate and is adjacent a second side of the gate structure opposite the first side. The drain region is in the double diffused region in the semiconductor substrate and is of a same conductivity type as the double diffused region. The first gate spacer is on the first side of the gate structure. The second gate spacer extends upwardly from the double diffused region along an outermost sidewall of the first gate spacer and terminates prior to reaching a top surface of the gate structure.

Abstract: A vehicle and a vehicle controlling method are provided. The vehicle includes a computing system; a vehicle controlling module coupled to the computing system; and a positioning module coupled to the computing system and the vehicle controlling module. The vehicle controlling module receives a safe stop path and a fusion coordinate from the computing system. When the vehicle controlling module determines that an abnormality occurs in the computing system, the vehicle controlling module receives a positioning coordinate from the positioning module and calculates an offset corresponding to the positioning coordinate and the fusion coordinate. The vehicle controlling module transmits a vehicle controlling command to the vehicle according to the offset and the safe stop path.

Abstract: An avalanche-protected field effect transistor includes, within a semiconductor substrate, a body semiconductor layer and a doped body contact region having a doping of a first conductivity type, and a source region a drain region having a doping of a second conductivity type. A buried first-conductivity-type well may be located within the semiconductor substrate. The buried first-conductivity-type well underlies, and has an areal overlap in a plan view with, the drain region, and is vertically spaced apart from the drain region, and has a higher atomic concentration of dopants of the first conductivity type than the body semiconductor layer. The configuration of the field effect transistor induces more than 90% of impact ionization electrical charges during avalanche breakdown to flow from the source region, to pass through the buried first-conductivity-type well, and to impinge on a bottom surface of the drain region.

Abstract: The present invention provides high affinity anti-CD40 monoclonal antibodies and related compositions, which may be used in any of a variety of therapeutic methods for the treatment of cancer and other diseases.

Abstract: The present invention provides high affinity anti-CD40 monoclonal antibodies and related compositions, which may be used in any of a variety of therapeutic methods for the treatment of cancer and other diseases.

Abstract: A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides for converting each respective signal to a respective analog voltage to drive a common node; and utilizing a charge storage device coupled to the common node to accumulate the respective analog voltages from the dice, where the accumulated voltage indicates total power consumption of the dice.