Patents by Inventor Lih-Jyh Weng

Lih-Jyh Weng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020095638
    Abstract: A method of determining error values including loading an error correction code (ECC) entity having rows representing data symbols, determining an error location for a first row, generating an error syndrome for the first row, determining an erasure constant array from the error location, determining an error location for each of the remaining rows, generating an error syndrome for each of the remaining rows and determining the error values for each of the rows from the corresponding error location and corresponding error syndrome and the constant.
    Type: Application
    Filed: November 30, 2000
    Publication date: July 18, 2002
    Inventors: Lih-Jyh Weng, Dana Hall
  • Patent number: 6389573
    Abstract: A read retrial mechanism which increases the error correction ability of a decoding operation by converting errors to erasures is presented. The mechanism reads at least two copies of a code word from memory and compares corresponding symbols to identify symbol locations for which corresponding symbols are of unequal value. At least one of the code word copies is decoded by an error-erasure decoding operation using the symbol locations identified by the comparison as erasures.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: May 14, 2002
    Assignee: Maxtor Corporation
    Inventor: Lih-Jyh Weng
  • Patent number: 6381726
    Abstract: A method and apparatus for decoding a corrupted code word is described. Decoding is accomplished by using a decoder that has a common measure of reliability for each symbol of the corrupted code word and determining whether a useful result can be obtained from the first decoder. If a useful result can not be obtained decoding the corrupted code word is accomplished with a second decoder that uses unique values of reliability for each symbol of the corrupted code word.
    Type: Grant
    Filed: January 4, 1999
    Date of Patent: April 30, 2002
    Assignee: Maxtor Corporation
    Inventor: Lih-Jyh Weng
  • Patent number: 6374383
    Abstract: A computation circuit for evaluating an error locator polynomial corresponding to a t-error correcting n-symbol code is described. In a first mode of operation, the computation circuit computes r syndromes in response to code word inputs. In a second mode of operation, the computation circuit is provided as inputs the coefficients of the error locator polynomial and evaluates the error locator polynomial for r location values in t+1 clock cycles. For each additional r location values, the inputs are the coefficients multiplied by a finite field element. The power of the finite field element is a multiple s of r. The value of the multiple s is initialized to one. After each next consecutive r location values are computed, sr+r is compared to n−1 and s is incremented prior to computing the next consecutive r location values if sr+1<n−1. If sr+r is ≧n−1, then no further computation of r location values is required.
    Type: Grant
    Filed: June 7, 1999
    Date of Patent: April 16, 2002
    Assignee: Maxtor Corporation
    Inventor: Lih-jyh Weng
  • Patent number: 6343367
    Abstract: An error correcting system for correcting “t” errors over GF(2m), where t is even and preferably greater than or equal to six, transforms the t-degree error locator polynomial c(x) into a polynomial t(x) in which at−1≈0, where ai is the coefficient of the xi term of the error locator polynomial and Tr(at−1)=1, where Tr(ai) is the trace of ai. The polynomial t(x) is factored into two factors, namely, one factor that is the greatest common divisor of t(x) and S ⁡ ( x ) = ∑ i = 0 m - 1 ⁢ x 2 i , and a second factor that is the greatest common divisor of t(x) and S(x)+1.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: January 29, 2002
    Assignee: Maxtor Corporation
    Inventors: Ba-Zhong Shen, Lih-Jyh Weng
  • Patent number: 6279023
    Abstract: A system for determining the multiplicative inverse of an element of GF(2m) by raising the element to the power 2m−2. The system may raise the element &agr;j to the power 2m−2 by repeatedly multiplying the element by itself 2m−3 times. Alternatively, the system may produce the exponent 2m−2 as the sum of: 2m−1+2m−2+ . . . +23+22+21 and thus (&agr;j)2m−2 as (&agr;j)2m−1*(&agr;j)2m−2* . . . *(&agr;j)23*(&agr;j)22*(&agr;j)2 The system may iteratively square &agr;j to produce the various factors (&agr;j)2m−1*(&agr;j)2m−2* . . . *(&agr;j)2 and, using a single multiplier, multiply and accumulate the results. Alternatively, the system may use a plurality of circuits operating in parallel and simultaneously raise the element &agr;j to the powers 2m−1, 2m−2 . . . 2 to produce the factors, and use a plurality of tiered multipliers to multiply the factors together.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: August 21, 2001
    Assignee: Maxtor Corporation
    Inventors: Lih-Jyh Weng, Ba-Zhong Shen
  • Patent number: 6260173
    Abstract: A combined encoding/syndrome generating circuit is segmented into multiple-cell blocks that operate in parallel during encoding operations to produce interim sums. The interim sums are then combined to propagate a sum across the system, from the first cell to the last cell. Each cell includes a Galois Field multiplier and an associated update adder and register. A block of two cells includes two sets of associated Galois Field multipliers, registers and update adders, and a block feedback adder that produces the associated interim sum by adding together the products produced in parallel by each of the cells. A block with more than two cells includes additional feedback adders that operate in parallel to selectively combine the products produced by the plurality of cells, and produce an interim sum that includes a contribution from each of the cells in the block. The system then adds together the interim sums produced simultaneously by the various blocks, to propagate a sum across the system.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: July 10, 2001
    Inventors: Lih-Jyh Weng, Ba-Zhong Shen, Shih Mo, Chung-Hsing Chang
  • Patent number: 6236340
    Abstract: A modulation encoder includes a base conversion circuit that converts a partitioned input data stream from a first base representation in accordance with the size of groups of bits in the partitioned stream into a second base representation. The base conversion circuit includes a circuit to produce intermediate values of the partitioned stream in the second base representation and a residual value logic circuit that performs modulo-arithmetic on intermediate values modulo the second base representation, and a one's complement logic network fed by the residual value logic to produce output code words. A modulation decoder includes a one's complement logic circuit fed by modulation code words to produces residual value words; and a base conversion circuit that converts residual value words from a first base representation into a second base representation to provide original user data.
    Type: Grant
    Filed: January 4, 1999
    Date of Patent: May 22, 2001
    Assignee: Quantum Corporation
    Inventors: Ara Patapoutian, Lih-Jyh Weng
  • Patent number: 6226772
    Abstract: An n-stage pipelined combined encoder and syndrome generator system includes n stages that are essentially identical. Each of the stages includes two associated delay circuits, namely, a first delay circuit in a chain of feedback adders that operate as a feedback path during encoding, and a second delay circuit in a data input line. During encoding operations, the delay circuits in the feedback adder chain segment the chain of j feedback adders into n stages of j/n adders, and the delay circuits in the data input line delay the data symbols by the latencies associated with the respective stages. The delay circuits thus simultaneously provide to the various stages the corresponding data symbols and propagating sums. After the last data symbol is encoded, the ECC symbols are available after a time lag associated with the j/n adders in the last stage.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: May 1, 2001
    Inventors: Lih-Jyh Weng, Diana Langer
  • Patent number: 6199088
    Abstract: A system for producing a quotient B/A, where A and B are elements of GF(22M), 2M+1 is prime and 2 is a primitive element of GF(2M+1), first determines A−1 and then multiplies B by A−1. The system uses a (2M+1)-bit representation for A and produces, directly from A, an element C=A2M+1, where C also is an element of GF(22M) which is a subfield of GF(2M). The system produces M+1 bits to represent C by performing bit manipulations that are equivalent to permuting the (2M+1)-bits to produce A2M and multiplying the permuted bits by A. The bit manipulations are: c0=&Sgr;aiai; c1=&Sgr;aiai+1 . . . cM=&Sgr;aiai+M where the aj's and cj's are the coefficients of A and C, respectively. The system retrieves C−1 from a (2M−1)-element lookup table and multiplies C−1=A−2M+1 by A2M to produce A−1.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: March 6, 2001
    Assignee: Quantum Corp.
    Inventors: Lih-Jyh Weng, Diana Langer
  • Patent number: 6199188
    Abstract: A system determines the locations of four errors in a code word over GF(2m), for any m, by transforming a degree-four error locator polynomial &sgr;(x) ultimately into two quadratic equations, finding the solutions of these equations, and from these solutions determining the roots of the error locator polynomial. The system first manipulates the degree-four error locator polynomial into a polynomial &thgr;(y) that has a coefficient of zero for the degree-three term. The system then factors this polynomial into two degree-two factors with four unknown variables. The system expands the factors and represents the coefficients of &thgr;(y) as expressions that include the four unknown variables, and manipulates the expressions to produce a degree-three polynomial with only one of the unknown variables. The system next solves for that variable by finding a root of the degree-three polynomial in GF(2m) if the field is an even-bit field or in an even-bit extension of GF(2m) if the field is an odd-bit field.
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: March 6, 2001
    Assignee: Quantum Corporation
    Inventors: Ba-Zhong Shen, Lih-Jyh Weng
  • Patent number: 6148430
    Abstract: An encoding/decoding system for RAID-6 or multiple track tape systems uses one of a selected set of values for m, with m+1 prime and the field GF(2.sup.m) generated by the irreducible polynomial:g(x)=x.sup.m +x.sup.m-1 + . . . +x.sup.2 +x+1.The system performs Galois Field multiplication operations as a combination of cyclic shifting and exclusive-OR operations, and determines multiplicative inverses of weight one, two and three (m+1)-bit symbols by raising various (m+1)-bit symbols to selected powers of two. Using this system, the value of m may be chosen to be as large as or larger than the sector or tape block, and the encoding and decoding is performed once per sector or block.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: November 14, 2000
    Assignee: Quantum Corporation
    Inventor: Lih-Jyh Weng
  • Patent number: 6044389
    Abstract: A system for determining the multiplicative inverse of an element of GF(2.sup.m) by raising the element to the power 2.sup.m -2. The system may raise the element .alpha..sup.j to the power 2.sup.m -2 by repeatedly multiplying the element by itself 2.sup.m -3 times. Alternatively, the system may produce the exponent 2.sup.m -2 as the sum of:2.sup.m-1 +2.sup.m-2 + . . . +2.sup.3 +2.sup.2 +2.sup.1and thus (.alpha..sup.j).sub.2.spsp.m.sup.-2 as(.alpha..sup.j).sup.2.spsp.m.sup.-1 *(.alpha..sup.j).sup.2.spsp.m.sup.-2 * . . . *(.alpha..sup.j).sup.2.spsp.3 *(.alpha..sup.j).sup.2.spsp.2 *(.alpha..sup.j).sup.2The system may iteratively square .alpha..sup.j to produce the various factors (.alpha..sup.j).sup.2.spsp.m.sup.-1 *(.alpha..sup.j).sup.2.spsp.m.sup.-2 * . . . *(.alpha..sup.j).sup.2 and, using a single multiplier, multiply and accumulate the results. Alternatively, the system may use a plurality of circuits operating in parallel and simultaneously raise the element .alpha..sup.j to the powers 2.sup.m-1, 2.sup.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: March 28, 2000
    Assignee: Quantum Corporation
    Inventors: Lih-Jyh Weng, Ba-Zhong Shen
  • Patent number: 5999959
    Abstract: A Galois field multiplier for GF(2.sup.n), with n=2m, multiplies two n-bit polynomials to produce a(x)*b(x)=a(x)b(x) mod g(x), where g(x) is a generator polynomial for the Galois field and "*" represents multiplication over the Galois field, by treating each polynomial as the sum of two m-bit polynomials:a(x)=a.sub.H (x)x.sup.m +a.sub.L (x) and b(x)=b.sub.H (x)x.sup.m +b.sub.L (x),witha.sub.H (x)x.sup.m =[a.sub.n-1 x.sup.(n-1)-m +a.sub.n-2 x.sup.(n-2)-m + . . . +a.sub.m+1 x.sup.(m+1)-m +a.sub.m ]x.sup.ma.sub.L (x)=a.sub.m-1 x.sup.m-1 +a.sub.m-2 x.sup.m-2 + . . . +a.sub.2 x.sup.2 +a.sub.1 x+a.sub.0and b.sub.H and b.sub.L having corresponding terms. Multiplying the two polynomials then becomes:a(x)*b(x)=(a.sub.H (x)x.sup.m +a.sub.L (x))*(b.sub.H (x)x.sup.m +b.sub.L (x))=[(a.sub.H (x)b(x).sub.H)x.sup.m mod g(x)+(b.sub.H (x)a.sub.L (x)+a.sub.L (x)b.sub.L (x))]x.sup.m mod g(x)+a.sub.L (x)b.sub.L (x).The Galois field multiplier produces four degree-(n-2) polynomial products, namely, a.sub.H (x)b.sub.H (x)=V.sub.
    Type: Grant
    Filed: February 18, 1998
    Date of Patent: December 7, 1999
    Assignee: Quantum Corporation
    Inventors: Lih-Jyh Weng, Ba-Zhong Shen, Diana Langer
  • Patent number: 5978956
    Abstract: An error correcting system transforms a degree-five error locator polynomial .sigma.(x) into the polynomial w(y)=y.sup.5 =b.sub.2 y.sup.2 +b.sub.1 y+b.sub.0, where b.sub.1 =0 or 1, and y=.sigma.(x), and determines the roots of .sigma.(x) based on the roots of w(y). The polynomial w(y) has (2.sup.M).sup.2 solutions over GF(2.sup.M), rather than (2.sup.M).sup.5 solutions, since for any solution with b.sub.2 =h.sub.2, b.sub.0 =h.sub.0 and b.sub.1 =1, there is no such solution with b.sub.2 =h.sub.2, b.sub.0 =h.sub.0 and b.sub.1 =0. Conversely, if there is such a solution with b.sub.1 =0 there are no such solutions with b.sub.1 =1. The system can thus use a table that has 2.sup.2M entries and is addressed by {b.sub.2, b.sub.0 }. The table produces roots y=r.sub.i, i=0, 1, 2, 3, 4, and the system then transforms the roots y=r.sub.i to the roots of .sigma.(x) by calculating x=.sigma..sup.-1 (y). To further reduce the overall table storage needs, the table may include in each entry four roots r.sub.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: November 2, 1999
    Assignee: Quantum Corporation
    Inventors: Lih-Jyh Weng, Ba-Zhong Shen
  • Patent number: 5948117
    Abstract: An error correction system includes an encoder that uses a modified Reed-Solomon code to encode w-bit data symbols over GF(2.sup.w+i) and form a preliminary code with d-1 (w+i+1)-bit redundancy symbols. The preliminary code word is modified as necessary to set for each symbol a selected i bits to the same value as a corresponding i+1.sup.st bit. The preliminary code word also includes R pseudo redundancy symbols that are required for decoding the modified code word. The i+1 bits are then truncated from each of the code word symbols, to form a code word with w-bit symbols. The Galois Field GF(2.sup.w+i) is selected such that the elements of the field can be represented by (w+i+1)-bit symbols that are determined by a polynomial h(x) modulo an irreducible polynomial p(x), which isp(x)=x.sup.w+i +x.sup.w+i-1 + . . . +x.sup.1 +x.sup.0,with the polynomial h(x) representing a primitive element.
    Type: Grant
    Filed: January 23, 1997
    Date of Patent: September 7, 1999
    Assignee: Quantum Corporation
    Inventors: Lih-Jyh Weng, Ba-Zhong Shen, Shih Mo
  • Patent number: 5901158
    Abstract: The encoder/decoder system uses encoder hardware to encode data symbols and form a data code word. To decode, the system uses the same encoder hardware to determine a residue r(x), i.e. ##EQU1## where C.sub.r (x) is the retrieved code word and g(x) is the generator polynomial. If the residue is all zeros, the ECC code word is error-free and the system need not calculate the error syndrome. If the residue is non-zero, the encoder hardware is used, with various switches in different settings, to include certain multipliers in and exclude other multipliers from the further decoding operations of encoding the residue symbols to produce partial error syndromes that are the coefficients of the error syndrome polynomial.
    Type: Grant
    Filed: April 22, 1997
    Date of Patent: May 4, 1999
    Assignee: Quantum Corporation
    Inventors: Lih-Jyh Weng, Ba-Zhong Shen, Shih Mo
  • Patent number: 5889794
    Abstract: A two-level error correction encoder encodes m-bit data symbols in a first level of encoding in accordance with a distance d ECC over GF(2.sup.m+i) to produce (m+i)-bit ECC redundancy symbols and, during a second level of encoding, both modifies the set of ECC redundancy symbols, as necessary, to set i selected bits in each symbol in a predetermined truncation pattern and appends to the set of ECC symbols one or more pseudo redundancy symbols. The encoder includes d-1 Galois Field multipliers, and d-1 associated redundancy-symbol registers and an ECC symbol modifier lookup table that has stored therein information that the encoder uses during the second level of encoding. After the first level of encoding, the d-1 registers contain the (m+i)-bit ECC redundancy symbols.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: March 30, 1999
    Assignee: Quantum Corporation
    Inventors: Shih Mo, Stanley Chang, Lih-Jyh Weng, Ba-Zhong Shen
  • Patent number: 5822336
    Abstract: An error correction system includes an encoder that uses a modified Reed-Solomon code to encode m-bit data symbols over GF(2.sup.m+i) and form a preliminary code with d-1 (m+i)-bit ECC symbols. The encoder then modifies the ECC symbols by combining the preliminary code word with a combination of one or more modifying code words to produce modified ECC symbols that have i bits set in a pre-selected pattern. This combination also results in "R" pseudo redundancy symbols that include the i-bit pattern being appended to the modified ECC symbols. The encoder truncates the i-bit pattern from each of the ECC symbols and the pseudo-redundancy symbols, to produce a data code word that has symbols that are elements of GF(2.sup.m).
    Type: Grant
    Filed: November 14, 1996
    Date of Patent: October 13, 1998
    Assignee: Quantum Corporation
    Inventors: Lih-Jyh Weng, Ba-Zhong Shen
  • Patent number: 5771246
    Abstract: A multiple-solid-burst error correcting system determines the number and locations of "solid burst" errors in a high-rate Reed Solomon or BCH code by determining the greatest common divisor of the error locator polynomial .sigma.(x), which has roots .alpha..sup.-i.sbsp.k that correspond to error locations i.sub.k, and a mapping error locator polynomial .sigma.(.alpha.*x) that maps the error locations , i.sub.k, to locations i.sub.k+1. The roots that are common to both polynomials, that is, the roots that are included in the greatest common divisor, d(x), correspond to adjacent error locations that are contained in the solid bursts. The roots of the non-common factors, p.sub.1 (x), of the error locator polynomial correspond to the first locations of the respective solid bursts and the roots of the non-common factors p.sub.2 (x) of the mapping error locator polynomial correspond to one location beyond the end locations of the solid bursts.
    Type: Grant
    Filed: September 17, 1996
    Date of Patent: June 23, 1998
    Assignee: Quantum Corporation
    Inventor: Lih-Jyh Weng