Patents by Inventor Lin Chen
Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250048686Abstract: The present disclosure provides an integrated circuit (IC) structure that includes a semiconductor substrate having a frontside and a backside; a shallow trench isolation (STI) structure formed in the semiconductor substrate and defining an active region, wherein the STI structure includes a STI bottom surface, wherein the semiconductor substrate includes a substrate bottom surface, and wherein the STI bottom surface and the substrate bottom surface are coplanar; a field-effect transistor (FET) over the active region and formed on the frontside of the semiconductor substrate; and a backside dielectric layer disposed on the substrate bottom surface and the STI bottom surface.Type: ApplicationFiled: January 11, 2024Publication date: February 6, 2025Inventors: Ping-Wei Wang, Gu-Huan Li, Jui-Lin Chen
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Publication number: 20250048763Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.Type: ApplicationFiled: October 21, 2024Publication date: February 6, 2025Inventors: Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Kuan-Chieh Huang, Jhy-Jyi Sze
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Publication number: 20250047189Abstract: A control device includes a first capacitor, a drive controller, a constant current source, a discharge-controlled current source, a current mirror, and a sample-and-hold circuit. The constant current source generates a constant current. The discharge-controlled current source is coupled to the constant current source and the first capacitor. The current mirror is coupled to the first capacitor and the primary side of a primary-side switch. The current mirror generates a copy current, thereby generating a copy voltage across the first capacitor. When the drive controller turns on the primary-side switch, the sample-and-hold circuit drives the discharge-controlled current source to sample and hold a control current from the constant current and the copy current. When the node voltage is higher than the copy voltage, the comparison circuit drives the drive controller to turn off the primary-side switch.Type: ApplicationFiled: October 24, 2023Publication date: February 6, 2025Inventors: KE-HORNG CHEN, YING-FENG WU, YU-CHOU KO, KUO-LIN ZHENG, KE-MING SU
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Publication number: 20250048062Abstract: Various arrangements disclosed herein relate to managing Multicast and Broadcast Services (MBSs) in various Radio Resource Control (RRC) states, including a wireless communication device receiving from a network using first signaling specific to the wireless communication device, PTM configuration used for receiving at least one MBS when the wireless communication device is in an RRC-connected state. The wireless communication device receives from the network using second signaling specific to the wireless communication device when the wireless communication device is in the RRC-connected state, indication information indicating that the PTM configuration used for receiving the at least one MBS is obtained from broadcast signaling when the wireless communication device is in an RRC-inactive state.Type: ApplicationFiled: October 25, 2024Publication date: February 6, 2025Applicant: ZTE CORPORATIONInventors: Yang LI, Tao QI, Lin CHEN
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Publication number: 20250046961Abstract: A lithium battery cell includes an upper cover module, a first battery electrode group, a second battery electrode group, and a plurality of first electrode connection straps. The first electrode connection straps are stacked together. A first end of the first electrode connection straps is welded to a first tab, a second end of the first electrode connection straps is welded to a second tab, and a middle part of the first electrode connection straps is welded to a first electrode terminal. An even number of first bending parts are formed between the middle part and the first end, and an even number of second bending parts are formed between the middle part and the second end, and the first bending parts and the second bending parts are symmetrical to each other. A lithium battery cell manufacturing method is also disclosed therein.Type: ApplicationFiled: October 25, 2024Publication date: February 6, 2025Inventors: Cheng-Huang CHEN, Yi-Hsiang CHAN, Shu-Lin CHEN, Wei-En HSU
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Publication number: 20250043045Abstract: A method for preparing a long-chain branched polypropylene includes subjecting a T-reagent to a polymerization reaction with propylene in the presence of a catalyst composition. The catalyst composition includes an alkylaluminoxane and a metallocene-based catalyst. The metallocene-based catalyst contains a metal selected from the group consisting of titanium (Ti), zirconium (Zr), and hafnium (Hf). The T-reagent having an alkenyl silyl functional group is selected from the group consisting of 1,2-bis[dimethyl(vinyl)silyl]ethane, dimethyldivinylsilane, 7-octenyldimethyl(vinyl)silane, 7-octenyldimethyl(allyl)silane, 4-(but-3-enyl)phenyldimethyl(vinyl)silane, 4-(but-3-enyl)phenyldimethyl(allyl)silane, and combinations thereof.Type: ApplicationFiled: July 30, 2024Publication date: February 6, 2025Inventors: Jing-Cherng Tsai, Kwang-Ming Chen, Jung-Hung Kao, Kun-Pei Hsieh, Chao-Shun Chang, Hsing-Chun Chen, Chun-Wei Chiu, Cheng-Hung Chiang, Yu-Chuan Sung, Shang-Lin Tsai, Yu-Sheng Lin
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Publication number: 20250042068Abstract: A method for processing a curved plastic panel is to first form a hard coating layer, an optical function layer, and a printing layer on a flat plastic substrate, and then cut it into a predetermined shape, and then use a hot pressing and curving device to perform a hot pressing and curving process to the flat plastic substrate in order to make it becoming a curved plastic substrate. The hot pressing and curving device can simultaneously perform hot pressing during the heating process, and has the functions of real-time monitoring of the local temperature and the local curvature forming state, and then feedback to the local heating and curvature forming mechanism for adjustments. The monitoring of temperature and curvature can be divided into multiple stages, which can be monitored stage by stage and adjusted for heating or curvature forming to improve production yield.Type: ApplicationFiled: October 20, 2024Publication date: February 6, 2025Applicant: ENFLEX CORPORATIONInventors: Hsin Yuan CHEN, Chih Teng KU, Jui Lin HSU, Chun Kai WANG, Yu Ling CHIEN
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Publication number: 20250048613Abstract: The present disclosure provides an IC structure that includes a semiconductor substrate having a SRAM region, an input/output and peripheral (IOP) region, and an edge region spanning tween the SRAM region and the IOP region; a STI structure formed on the semiconductor substrate and defining active regions; a SRAM cell formed within the SRAM region; and a backside dielectric layer disposed on a backside of the semiconductor substrate and landing on a bottom surface of the STI structure. The active regions are longitudinally oriented along a first direction; gates are formed on the semiconductor substrate and are evenly distributed with a pitch P along the first direction; the SRAM cell spans a first dimension Ds along the first direction; the edge region spans a second dimension De along the first direction; and a ratio De/Ds equals to 2 or is less than 2.Type: ApplicationFiled: January 12, 2024Publication date: February 6, 2025Inventors: Jui-Lin Chen, Feng-Ming Chang, Ping-Wei Wang, Yu-Bey Wu
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Publication number: 20250048624Abstract: The present disclosure provides embodiments of electronic fuse devices. An electronic fuse device according to the present disclosure includes a first bit cell comprising a first plurality of active regions extending along a first direction and a second bit cell comprising a second plurality of active regions extending along the first direction. Each of the first plurality of active regions is aligned with one of the second plurality of active regions along the first direction. The first bit cell and the second bit cell are spaced apart along the first direction by a space and the space is free of a well tap cell.Type: ApplicationFiled: October 17, 2023Publication date: February 6, 2025Inventors: Jui-Lin Chen, Meng-Sheng Chang, Ping-Wei Wang
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Publication number: 20250048166Abstract: A wireless communication method for use in a first wireless terminal is disclosed. The method comprises receiving, from a first wireless network node, a sidelink (SL) measurement configuration associated with a user-to-user relay for the first wireless terminal and a second wireless terminal, and transmitting, to the first wireless network node, a measurement report based on the measurement configuration.Type: ApplicationFiled: October 25, 2024Publication date: February 6, 2025Applicant: ZTE CORPORATIONInventors: Mengzhen WANG, Lin CHEN, Wanfu XU, Weiqiang DU, Tao QI
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Publication number: 20250048612Abstract: An integrated circuit (IC) device has a memory region in which a plurality of memory cells is implemented. Each of the memory cells has a first dimension in a first horizontal direction. The IC device includes an edge region bordering the memory cell region in the first horizontal direction. The edge region has a second dimension in the first horizontal direction. The second dimension is less than or equal to about 4 times the first dimension. The IC device is formed by revising a first IC layout to generate a second IC layout. The second IC layout is generated by shrinking a dimension of the edge region in the first horizontal direction.Type: ApplicationFiled: January 4, 2024Publication date: February 6, 2025Inventors: Jui-Lin Chen, Feng-Ming Chang, Ping-Wei Wang, Yu-Bey Wu, Chih-Ching Wang
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Patent number: 12218160Abstract: A pixel sensor may include a layer stack to reduce and/or block the effects of plasma and etching on a photodiode and/or other lower-level layers. The layer stack may include a first oxide layer, a layer having a band gap that is approximately less than 8.8 electron-Volts (eV), and a second oxide layer. The layer stack may reduce and/or prevent the penetration and absorption of ultraviolet photons resulting from the plasma and etching processes, which may otherwise cause the formation of electron-hole pairs in the substrate in which the photodiode is included.Type: GrantFiled: March 12, 2021Date of Patent: February 4, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Lin Chen, Ching-Chung Su, Chun-Hao Chou, Kuo-Cheng Lee
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Patent number: 12218884Abstract: This disclosure provides methods, devices and systems for increasing the transmit power of wireless communication devices operating on power spectral density (PSD)-limited wireless channels. Some implementations more specifically relate to short training field (STF) designs and signaling that support distributed transmissions. A transmitting device that transmits data on a distributed resource unit (dRU) may transmit an STF sequence over a spreading bandwidth of the dRU according to an existing STF tone plan. Each STA allocated a dRU for transmission in a trigger-based (TB) physical layer convergence protocol (PLCP) protocol data unit (PPDU) maps its STF sequence to one or more spatial streams and may apply one or more global cyclic shift delays (CSDs) to the STF sequence mapped to the one or more spatial streams, respectively. As such, different global CSDs may be assigned to different STAs so that each STA transmits its STF sequence with different amounts of delay.Type: GrantFiled: October 15, 2021Date of Patent: February 4, 2025Assignee: QUALCOMM IncorporatedInventors: Lin Yang, Bin Tian, Youhan Kim, Qifan Chen
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Patent number: 12217163Abstract: Methods and systems for budgeted and simplified training of deep neural networks (DNNs) are disclosed. In one example, a trainer is to train a DNN using a plurality of training sub-images derived from a down-sampled training image. A tester is to test the trained DNN using a plurality of testing sub-images derived from a down-sampled testing image. In another example, in a recurrent deep Q-network (RDQN) having a local attention mechanism located between a convolutional neural network (CNN) and a long-short time memory (LSTM), a plurality of feature maps are generated by the CNN from an input image. Hard-attention is applied by the local attention mechanism to the generated plurality of feature maps by selecting a subset of the generated feature maps. Soft attention is applied by the local attention mechanism to the selected subset of generated feature maps by providing weights to the selected subset of generated feature maps in obtaining weighted feature maps.Type: GrantFiled: September 22, 2023Date of Patent: February 4, 2025Assignee: Intel CorporationInventors: Yiwen Guo, Yuqing Hou, Anbang Yao, Dongqi Cai, Lin Xu, Ping Hu, Shandong Wang, Wenhua Cheng, Yurong Chen, Libin Wang
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Patent number: 12216980Abstract: A method includes the following operations: identifying a layer of a first layout based on a first violation generated on the layer; generating a metal density value associated with the layer; when the metal density value is larger than or equal to a preset value, classifying the first violation into a first class corresponding to routing congestions of the first layout; when the first violation is classified into the first class, assigning, to the first violation, a first operation of a plurality of first pre-stored operations corresponding to the first class; and performing the first operation to the first layout to generate a second layout.Type: GrantFiled: July 27, 2022Date of Patent: February 4, 2025Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., TSMC NANJING COMPANY LIMITEDInventors: Yi-Lin Chuang, Song Liu, Pei-Pei Chen, Heng-Yi Lin, Shih-Yao Lin, Chin-Hsien Wang
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Publication number: 20250040235Abstract: A method for manufacturing an integrated circuit device is provided. The method includes depositing an epitaxial stack comprising alternative first and second semiconductor layers over a semiconductor substrate; patterning the epitaxial stack to form first and second semiconductor fins; removing the first semiconductor layers in the first and second semiconductor fins, while leaving a first set of the second semiconductor layers in the first semiconductor fin and a second set of the second semiconductor layers in the second semiconductor fin; forming a gate dielectric layer around the first and second sets of the second semiconductor layers; depositing a gate metal layer over the gate dielectric layer; etching a recess in the gate metal layer and between the first and second sets of the second semiconductor layers, wherein the gate metal layer has a first portion below the recess; and forming a dielectric feature in the recess.Type: ApplicationFiled: July 25, 2023Publication date: January 30, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Jung-Chien Cheng, Shi Ning Ju, Chih-Hao Wang
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Publication number: 20250036953Abstract: In some example embodiments, there may be provided a method that includes receiving, at a machine learning model, an input for a task of the machine learning model, wherein the machine learning model comprises a plurality of residual blocks augmented with a plurality of augmented weight blocks that sample intermediate features from the plurality of residual blocks; applying the input to the machine learning model to perform the task, wherein the applying comprises applying the plurality of intermediate features, which are obtained from the plurality of residual blocks, to the plurality of augmented weight blocks to form a plurality of intermediate outputs; and generating an output of the machine learning model, wherein the output is generated using at least on a combination of the plurality of intermediate outputs. Related systems, methods, and articles of manufacture are also disclosed.Type: ApplicationFiled: December 5, 2022Publication date: January 30, 2025Inventors: Harinath Garudadri, Kuan-Lin Chen, Bhaskar D. Rao, Ching-Hua Lee
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Publication number: 20250035829Abstract: A coated textured glass article is described herein that comprises: a glass body comprising a first surface; a plurality of polyhedral surface features extending from the first surface; and a coating disposed on the first surface of the body and the plurality of polyhedral surface features. Each of the plurality of polyhedral surface features comprises a base on the first surface and a plurality of facets extending from the base and converging toward one another. The coating comprises a multilayer interference stack.Type: ApplicationFiled: February 20, 2023Publication date: January 30, 2025Inventors: Jaymin Amin, Xinyu Cao, Ling Chen, Wanghui Chen, Jiangwei Feng, Robert Randall Hancock, Jr., Shandon Dee Hart, Yuhui Jin, Karl William Koch, III, Carlo Anthony Kosik Williams, Aize Li, Lin Lin, Loretta Jane Moses, Meng Shang, Nicholas Michael Walker
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Publication number: 20250037273Abstract: A method of estimating a distance in an endoscopic image is implemented by an endoscopic system. The method includes steps of: irradiating a lesion of a subject and obtaining an image of the lesion and a scale of the endoscopic system as a to-be-analyzed image while the lesion is being irradiated and the scale is placed adjacent to the lesion; using a lesion-contour prediction model to generate a prediction result that indicates a contour of the lesion; displaying the prediction result; generating two selected points on the contour of the lesion; and estimating, based on the scale in the to-be-analyzed image, an actual distance between the two selected points.Type: ApplicationFiled: May 17, 2024Publication date: January 30, 2025Inventors: Po-Wen LU, Xiu-Zhi CHEN, Yen-Lin CHEN
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Patent number: D1060911Type: GrantFiled: June 6, 2023Date of Patent: February 4, 2025Assignee: Tiedeping Hardware Plastic (Shenzhen) Co., Ltd.Inventors: Dongfang Chen, Lin Liang