Patents by Inventor Lin Chen

Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12364974
    Abstract: The present invention relates to a particulate filter, in particular a particulate filter for use in an emission treatment system of an internal combustion engine. The particulate filter provides an advantageous combination of low back pressure and high fresh filtration efficiency.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: July 22, 2025
    Assignee: BASF Corporation
    Inventors: Jun Cong Jiang, Yun Fei Qi, Attilio Siani, Weiyong Tang, Shau Lin Chen
  • Patent number: 12369182
    Abstract: A system and method for reference signaling design and configuration are disclosed herein. In one embodiment, the system and method are configured to receive, by a first wireless communication device from a wireless communication node, configuration information of a sidelink medium access control (MAC) control element (CE). The system and method are also configured to transmit, by the first wireless communication device according to the configuration information, the sidelink MAC CE to a second wireless communication device.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: July 22, 2025
    Assignee: ZTE Corporation
    Inventors: Wei Luo, Boyuan Zhang, Lin Chen
  • Publication number: 20250234578
    Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according to one embodiment of the present disclosure includes forming a plurality of semiconductor nanostructures vertically stacked above a substrate, forming a dielectric structure suspended above a topmost one of the semiconductor nanostructures, forming a plurality of inner spacers interleaving the semiconductor nanostructures, forming an epitaxial feature abutting the semiconductor nanostructures, and forming a gate structure wrapping around each of the semiconductor nanostructures and the dielectric structure.
    Type: Application
    Filed: July 5, 2024
    Publication date: July 17, 2025
    Inventors: Jung-Chien Cheng, Guan-Lin Chen, Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20250234595
    Abstract: Inner spacers between a source/drain region of a nanostructure transistor and sacrificial nanostructure layers of the nanostructure transistor are removed prior to formation of a gate structure of the nanostructure transistor. The sacrificial nanostructure layers are removed, and then the inner spacers are removed. The sacrificial nanostructure layers are then replaced with the gate structure of the nanostructure transistor such that the gate structure and the source/drain region are spaced apart by air gaps that result from the removal of the inner spacers. The dielectric constant (or relative permittivity) of the air gaps between the source/drain region and the gate structure is less than the dielectric constant of the material of the inner spacers. The lesser dielectric constant of the air gaps reduces the amount of capacitance between the source/drain region and the gate structure.
    Type: Application
    Filed: May 22, 2024
    Publication date: July 17, 2025
    Inventors: Hsien-Chih HUANG, Guang-Lin CHEN, Pei-Yu WANG, Chia-Hao YU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 12361734
    Abstract: The present application discloses a method for detecting image by using semantic segmentation. To input an image with data augmentation, and then encode and decode using a neural network. At least one semantically divided, and finally the at least one semantically divided is compared with the sample to classify as a target or a non-target. In this way, the CNN is used to detect whether the image is the SCC image or not, and locate the section, thereby assisting the doctor in interpreting the esophagus image.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: July 15, 2025
    Assignee: National Chung Cheng University
    Inventors: Hsiang-Chen Wang, Kuan-Lin Chen, Yu-Ming Tsao, Jen-Feng Hsu
  • Patent number: 12363562
    Abstract: This disclosure relates to methods and devices for routing and bearer mapping configuration in an integrated access and backhaul (IAB) network. In one implementation, the method may include detecting, by an IAB entity, a failure in transmitting a packet via an egress link of an original routing path. The method may further include selecting, by the IAB entity, a backhaul adaption protocol routing identifier of a backup routing path for the packet. The method may further include selecting, by the IAB entity, an egress backhaul radio link control channel on an egress link of the backup routing path for transmitting the packet.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: July 15, 2025
    Assignee: ZTE Corporation
    Inventors: Lin Chen, Wei Luo, Mengzhen Wang, Wei Zou, Xueying Diao
  • Patent number: 12363753
    Abstract: Provided are a resource request method and device, and the method includes: transmitting low latency traffic information to a network control unit; and receiving resource allocation information formed from resource allocation performed by the network control unit based on the low latency traffic information. Embodiments of the present disclosure provide a computer storage medium.
    Type: Grant
    Filed: October 20, 2023
    Date of Patent: July 15, 2025
    Assignee: ZTE Corporation
    Inventors: Wei Luo, Lin Chen
  • Patent number: 12363969
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.
    Type: Grant
    Filed: January 5, 2024
    Date of Patent: July 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
  • Publication number: 20250225280
    Abstract: A computing system includes a drawer configured to receive a plurality of computing storage devices. The drawer is movable between an open position and a plurality of closed positions. A printed circuit board (PCB) is mounted within the drawer in electronic communication with the plurality of computing devices. An intrusion-detection switch is attached to the PCB and is configured to detect movement of the drawer between the open position and the closed positions. A rotating module is attached to the movable drawer for extending an operating range of the intrusion-detection switch. The rotating module is in initial contact with the intrusion-detection switch when the drawer is in the initial closed position. The rotating module has a rotating unit that rotates in response to the drawer moving from an initial closed position to a maximum closed position.
    Type: Application
    Filed: January 4, 2024
    Publication date: July 10, 2025
    Inventors: Yaw-Tzorng TSORNG, Ming-Lung Wang, Jia-Lin Chen
  • Publication number: 20250227907
    Abstract: A semiconductor device includes: a first memory array with a first side; a second memory array with a second side that faces the first side; and a well pickup region between the first memory array along the first side and the second memory array along the second side, the well pickup region having a first region and a second region each with an n-well tap cell and a middle region with a p-well tap cell between the first region and the second region, wherein a first edge region of the first region is placed along the first side of the first memory array region and a second edge region of the second region is placed along the second side of the second memory array region; wherein the p-well tap cell includes a contiguous OD region for providing reverse bias to P-N junctions in the first and second memory array regions.
    Type: Application
    Filed: January 8, 2024
    Publication date: July 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Wen Chang, Feng-Ming Chang, Jui-Lin Chen, Lien-Jung Hung, Ping-Wei Wang
  • Patent number: 12352324
    Abstract: A clutch can include an input; an output; a centrifugal clutch mechanism that transfers energy from the input to the output, the centrifugal clutch mechanism including: a disk; centrifugal weights movably coupled to the disk; and a central shaft rotatable relative to the disk and extending through the disk, the central shaft comprising drive surfaces, wherein the disk is rotatably coupled to the input, wherein the output is rotatably coupled to the central shaft, wherein the centrifugal weights rotate between a disengaged position in which the centrifugal weights do not interface with drive surfaces and an engaged position in which the centrifugal weights interface with the drive surfaces, and wherein the centrifugal weights are disposed inside the perimeter of the disk when the centrifugal weights are in the engaged position.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: July 8, 2025
    Assignee: Milwaukee Electric Tool Corporation
    Inventors: Kevin S. Puls, Beth E. Cholst, Casey D. Garces, Tyler J. Reaker, Brian J. Yue, Kang Lin Chen, Jie Wang
  • Patent number: 12355170
    Abstract: A modular riser card, an electronic device having a modular riser card, and a method of determining a type of modular riser card pin connection are disclosed. The modular riser card includes a circuit board and a removable connector assembly. The circuit board includes a first receptacle having a plurality of first pins. The removable connector assembly includes a connector body defining a second receptacle having a plurality of second pins, and an opening formed in the connector body adjacent to the second receptacle. The connector body is mounted on the circuit board such that the first receptacle protrudes through the opening and is aligned with the second receptacle. The first and second receptacles form a riser card connector that is configured to removably receive an expansion card of an electronic device.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: July 8, 2025
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Kuan-Wei Chen, Vincent Nguyen, Ku-Hsu Nien, Jui Lin Chen, Hsueh Yu Chao
  • Publication number: 20250220871
    Abstract: A semiconductor device according to the present disclosure includes a first memory cell and a second memory cell. The first memory cell includes a first active region for n-type transistors and a second active region for p-type transistors. The first active region has a first width. The second active region has a second width. The first width is larger than the second width. The second memory cell includes a third active region for n-type transistors and a fourth active region for p-type transistors. The third active region has a third width. The fourth active region has a fourth width. The third width is larger than the fourth width. The first width is larger than the third width.
    Type: Application
    Filed: June 12, 2024
    Publication date: July 3, 2025
    Inventors: Ping-Wei Wang, Feng-Ming Chang, Jui-Lin Chen
  • Publication number: 20250220845
    Abstract: A computing system includes a drawer configured to receive a plurality of computing storage devices. The drawer is movable between an open position and a plurality of closed positions. A printed circuit board (PCB) is mounted within the drawer in electronic communication with the plurality of computing devices. An intrusion-detection switch is attached to the PCB and is configured to detect movement of the drawer between the open position and the closed positions. A pressing module is attached to the movable drawer for extending an operating range of the intrusion-detection switch. The pressing module is in initial contact with the intrusion-detection switch when the drawer is in the initial closed position. The pressing module has a pressing unit that translates linearly in response to the drawer moving from an initial closed position to a maximum closed position.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Inventors: Yaw-Tzorng TSORNG, Ming-Lung WANG, Jia-Lin CHEN
  • Publication number: 20250218463
    Abstract: A book assembly with internal electronics. The book assembly has the structure of a book with a front cover, a rear cover, and at least one page. A plurality of touch sensors are disposed within the book with at least some of the pages containing a touch sensor. A microphone and speaker are supported by the book assembly and are usable with the book assembly being either open or closed. The book assembly contains circuitry for recording and storing custom audio files made via the microphone. The circuity can also hold preset audio files that come with the book assembly. At least one control switch is accessible on the book structure for selecting between a recording mode and a play mode. In the recording mode, the circuitry records a custom audio file for each of said plurality of touch sensors. The custom audio recording is assigned to the touch sensor that is activated at the time of the recording.
    Type: Application
    Filed: July 17, 2024
    Publication date: July 3, 2025
    Inventor: Jen-Lin Chen
  • Patent number: 12347486
    Abstract: A forming method of a ReRAM array includes steps as follows: Firstly, a first pulse is applied to a first ReRAM unit in the ReRAM array. Afterwards, a second pulse is applied to the first ReRAM unit, wherein the electrical property of the first pulse is opposite to that of the second pulse. Then, a verification pulse is applied to the first ReRAM unit to verify whether the first resistance value of the first ReRAM unit passes a preset threshold. When the first resistance value passes the preset threshold value, a third pulse is applied to the first ReRAM unit, wherein the first pulse and the third pulse have the same electrical property, and the first pulse has a voltage value substantially the same to that of the third pulse.
    Type: Grant
    Filed: May 24, 2023
    Date of Patent: July 1, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsiu Hsu, Yu-Huan Yeh, Cheng-Hsiao Lai, Guan-Lin Chen, Chuan-Fu Wang, Hung-Yu Fan Chiang
  • Publication number: 20250212250
    Abstract: A wireless communication method is disclosed. The method comprises performing, by a first wireless communication terminal, a detection for a consistent listen-before-talk, LBT, failure of a sidelink transmission on one or more sidelink resource sets; and performing, by the first wireless communication terminal, at least one of the following operations in response to the consistent LBT failure of the sidelink transmission being detected on a first sidelink resource set of the one or more sidelink resource sets: setting the first sidelink resource set as an unavailable sidelink resource set, and then setting the first sidelink resource set as an available sidelink resource set in response to one or more predetermined conditions being met; or transmitting, to a second wireless communication terminal, a consistent LBT failure indication via a second sidelink resource set.
    Type: Application
    Filed: December 18, 2024
    Publication date: June 26, 2025
    Applicant: ZTE CORPORATION
    Inventors: Wei LUO, Lin CHEN, Weiqiang DU
  • Publication number: 20250207031
    Abstract: An LC medium (as a subcategory of liquid crystal material) comprising two or more polymerizable compounds, its use for optical, electro-optical and electronic purposes, in particular in LC displays, especially in LC displays of the PSA (polymer sustained alignment) or SA (self-aligning) mode, an LC display of the PSA or SA mode comprising the LC medium, and a process of manufacturing the LC display using the LC medium, especially an energy-saving LC display and energy-saving LC display production process.
    Type: Application
    Filed: December 19, 2024
    Publication date: June 26, 2025
    Applicant: MERCK PATENT GmbH
    Inventors: Min Tzu Chuang, I-Wen Chen, I-Hua Huang, Jer-Lin Chen, Sven Christian Laut
  • Publication number: 20250195580
    Abstract: The present disclosure relates to a cell protein extract having cell repair effect. The preparation thereof includes the following steps: (1) placing mesenchymal passage cells with a density of 1.0×106 cells/mL to 5.0×107 cells/mL in a culture medium containing DMEM/F12 40-50%, RPMI1640 40-50%, bovine serum albumin (BSA) 0.1-2%, epidermal growth factor (EGF) 1-15 ?g/mL, fibroblast growth factor (FGF) 1-15 ?g/mL, insulin transferrin 1-15 ?g/mL, compound amino acids (18AA) 0.01-0.1%, and 2-10 ?mol/L of a stressor, and then culturing the cells under conditions of 37.0° C.±0.5° C. and 5%±1.0% CO2 for 10 minutes to 14 hours, and then performing isolation, washing, and collecting cells, wherein the stressor is selected from any one of compounds 1-16 or a combination thereof; (2) performing an ultrasonic treatment on the collected cells at 2° C.-8° C. to prepare a cell lysate, and filtering same so as to obtain the cell protein extract.
    Type: Application
    Filed: January 28, 2023
    Publication date: June 19, 2025
    Inventors: Yu WANG, Wenyong GAO, Lin CHEN, Jianjun LI
  • Publication number: 20250204007
    Abstract: The invention provides a semiconductor structure, which comprises a substrate, a high-voltage device region is defined on the substrate, in the high-voltage device region, the substrate comprises a first region, a first groove surrounds the first region, and a second region surrounds the first groove, and a contact gate structure is located in the high-voltage device region, when viewed from a top view, the contact gate structure comprises a plurality of columnar dielectric layers arranged in an array.
    Type: Application
    Filed: January 16, 2024
    Publication date: June 19, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Chun-Wen Cheng, Ming-Hua Tsai, Chun-Lin Chen, Ming-Hsiang Tu, Ya-Hsin Huang, Yung-Fang Yang