Patents by Inventor Lin Chen

Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11996137
    Abstract: A memory device for CIM has a memory array including a plurality of memory cells arranged in an array of rows and columns. The memory cells have a first group of memory cells and a second group of memory cells. Each row of the array has a corresponding word line, with each memory cell of a row of the array coupled to the corresponding word line. Each column of the array has a corresponding bit line, with each memory cell of a column of the array coupled to the corresponding bit line. A control circuit is configured to select the first group of memory cells or the second group of memory cells in response to a group enable signal.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-An Chang, Yu-Lin Chen, Chia-Fu Lee
  • Patent number: 11993686
    Abstract: The present application discloses a surface treatment method of a polymer for 5G, belonging to the technical field of surface treatment of polymer. By injecting and adding the oxygen elements to the polymer, the polymer matrix elements and the injected atoms can form a blend structure, which can increase the surface roughness of the polymer, improve its bonding strength with the metal, and thus enhance its anti-peel strength. The surface treatment method of the application has the surface resistivity, surface roughness, water absorption and tensile properties of the polymer all considered. The equipment used in the invention has long service life and low cost, and can realize large-scale roll-to-roll production. The method can be popularized in polymer surface treatment.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: May 28, 2024
    Assignees: Beijing Normal University, Guangdong Guangxin Ion Beam Technology Co., Ltd.
    Inventors: Bin Liao, Xiao Ouyang, Guoliang Wang, Xiaoping Ouyang, Jun Luo, Pan Pang, Lin Chen, Xu Zhang, Xianying Wu, Minju Ying
  • Publication number: 20240172255
    Abstract: In some aspects, a wireless communication method includes: determining, by a wireless communication device, whether at least one of a dedicated resource pool or a number of shared resource pools is provided, wherein each of the shared resource pools includes a sidelink transmission or reception resource pool; and performing, by the wireless communication device, sidelink discovery using the dedicated resource pool or one of the shared resource pools being provided based on its configuration.
    Type: Application
    Filed: January 31, 2024
    Publication date: May 23, 2024
    Applicant: ZTE Corporation
    Inventors: Wei LUO, Weiqiang DU, Lin CHEN
  • Publication number: 20240172085
    Abstract: Methods, systems, apparatus for wireless communication are described. A method of wireless communication is provided to include performing, by a first node of an integrated access and backhaul (IAB) network, a data transmission with a second node in the IAB. In addition, apparatus for implementing the method is also described.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Inventors: Xueying DIAO, Lin CHEN, Ying HUANG
  • Publication number: 20240166711
    Abstract: The present application provides a method for promoting the sternness and/or transdifferentiation of acinar cells, comprising the following steps: providing an acinar cell, transfecting a plasmid into the acinar cell, and culturing the transfected acinar cell, wherein the plasmid contains a genetic material for overexpression of N-acetylglucosaminyltransferase V (GnT-V).
    Type: Application
    Filed: November 18, 2022
    Publication date: May 23, 2024
    Inventors: Pei-Jen Lou, Tai-Horng Young, Ching-Chia Cheng, Mei-Chun Lin, Hisn-Lin Chen
  • Publication number: 20240166789
    Abstract: The present invention provides a conjugated diene based rubber comprising a conjugated diene based copolymer comprising at least two conjugated diene monomer units and optionally comprising a vinyl aromatic hydrocarbon monomer unit, wherein the conjugated diene based copolymer comprises a first block composed of a first conjugated diene monomer unit and the vinyl aromatic hydrocarbon monomer unit or a second conjugated diene monomer unit, the second conjugated diene monomer unit being distinct from the first conjugated diene monomer unit, the first block being random; and a second block, comprising at least the second conjugated diene monomer unit and optionally comprising the vinyl aromatic hydrocarbon monomer unit, wherein the first block is connected to the second block, and the amount of the vinyl aromatic hydrocarbon monomer units or the second conjugated diene monomer units is at least 35 wt % of the first block.
    Type: Application
    Filed: November 17, 2023
    Publication date: May 23, 2024
    Applicant: TSRC Corporation
    Inventors: Chun-Lin Chen, Yun-Ta Lee
  • Patent number: 11988711
    Abstract: A test circuit includes a scan chain and a wrapper chain. The wrapper chain shifts in a test pattern according a first clock. The scan chain is coupled to the wrapper chain via a logic combination of a circuit under test. The wrapper chain is configured to transmit the test pattern to the scan chain via the logic combination according to a second clock in a capture phase. The wrapper chain includes a first, a second wrapper cell, and an asynchronous register. The first wrapper cell sequentially shifts in two bits of the test pattern in the shift-in phase. The second wrapper cell shifts in the first bit of the test pattern in the shift-in phase. The asynchronous register conducts the first wrapper cell to the second wrapper cell in the shift-in phase, and latches the second wrapper cell in the capture phase.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: May 21, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Po-Lin Chen, Chun-Teng Chen
  • Patent number: 11990471
    Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Ting Pan, Chih-Hao Wang
  • Patent number: 11990488
    Abstract: A grid structure in a pixel array may be at least partially angled or tapered toward a top surface of the grid structure such that the width of the grid structure approaches a near-zero width near the top surface of the grid structure. This permits the spacing between color filter regions in between the grid structure to approach a near-zero spacing near the top surfaces of the color filter regions. The tight spacing of color filter regions provided by the angled or tapered grid structure provides a greater surface area and volume for incident light collection in the color filter regions. Moreover, the width of the grid structure may increase at least partially toward a bottom surface of the grid structure such that the wider dimension of the grid structure near the bottom surface of the grid structure provides optical crosstalk protection for the pixel sensors in the pixel array.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Lin Chen, Ching-Chung Su, Chun-Hao Chou, Kuo-Cheng Lee
  • Patent number: 11989426
    Abstract: Systems, apparatus and methods are provided for power management of non-volatile storage (NVM) systems. A non-volatile storage system may include a first interface to be coupled to a host, a NVM device, a storage controller including a command queue and a processor, and a second interface coupling the storage controller and the NVM device. The processor may be configured to handle data transfer requests from the host in an active power state, monitor the command queue and a data transfer rate on the first interface, determine that the data transfer rate falls below a predetermined threshold and the command queue is empty, enter a pseudo-idle power state, determine that there is a new command from the host, and exit the pseudo-idle power state and enter the active power state.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: May 21, 2024
    Assignee: Innogrit Technologies Co., Ltd.
    Inventors: Gang Zhao, Ming Lu, Lin Chen
  • Patent number: 11990339
    Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang
  • Patent number: 11991317
    Abstract: According to some embodiments, a method performed by a software defined wide area network (SD-WAN) controller communicably coupled to a voice gateway comprises determining a user profile from one or more stored user profiles is to be associated with an analog telephone and transmitting the user profile to the voice gateway. In particular embodiments, the SD-WAN controller may receive a request to associate the analog telephone with a user from the voice gateway.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: May 21, 2024
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Haitao Zhang, Chang-Ho Lin, Jing Li, Ming Lin Chen, Nanditha Shenoy
  • Publication number: 20240158550
    Abstract: The disclosure provides a vinyl-containing aromatic alicyclic copolymer, a resin composition and a product thereof. The resin composition includes the vinyl-containing aromatic alicyclic copolymer, and the product made of the resin composition has a Tg of greater than 200° C., a dielectric constant Dk (10 GHz) of less than 3.0 and a dielectric loss Df (10 GHz) of less than 0.0014.
    Type: Application
    Filed: December 6, 2022
    Publication date: May 16, 2024
    Applicant: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Chi-Lin Chen
  • Publication number: 20240162227
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The method includes forming a first dielectric feature between first and the second fin structures, wherein each first and second fin structure includes first semiconductor layers and second semiconductor layers alternatingly stacked and in contact with the first dielectric layer. The method also includes removing the second semiconductor layers so that the first semiconductor layers of the first and second fin structures extend laterally from a first side and a second side of the first dielectric feature, respectively, trimming the first dielectric feature so that the first dielectric feature has a reduced thickness on both first and the second sides, and forming a gate electrode layer to surround each of the first semiconductor layers of the first and second fin structures.
    Type: Application
    Filed: November 19, 2023
    Publication date: May 16, 2024
    Inventors: Guan-Lin CHEN, Kuo-Cheng CHIANG, Shi Ning JU, Jung-Chien CHENG, Chih-Hao WANG, Kuan-Lun CHENG
  • Patent number: 11984400
    Abstract: An SRAM device and method of forming include pass gate (PG), pull-down (PD), and pull-up (PU) transistors. A first gate line of the PG and a second gate line of the PD and the PU extend in a first direction. A common source/drain of the PG, PD, and PU transistors interposes the first and second gate lines and another source/drain of the PG transistor. A first contact extends from the common source/drain and a second contact extends from the another source/drain. A third contact is disposed above the second contact with a first width in the first direction and a first length in a second direction, first length being greater than the first width.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Yuan Chang, Jui-Lin Chen, Kian-Long Lim, Feng-Ming Chang
  • Patent number: 11980763
    Abstract: A system for validating safety of a medical device in a presence of a magnetic resonance imaging (MRI) field is provided. The system includes a first electric field generating device configured to form first electric field and configured to receive a medical device at least partially within the first electric field, and a second electric field generating device configured to form a second electric field in proximity to the first electric field and configured to receive the medical device at least partially within the second electric field.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: May 14, 2024
    Assignee: Pacesetter, Inc.
    Inventors: Xi Lin Chen, Xiyao Xin, Shiloh Sison, Shi Feng
  • Patent number: 11984488
    Abstract: Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Chih-Hao Wang, Kuan-Lun Cheng
  • Publication number: 20240154015
    Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.
    Type: Application
    Filed: March 22, 2023
    Publication date: May 9, 2024
    Inventors: Jui-Lin CHEN, Hsin-Wen SU, Chih-Ching WANG, Chen-Ming LEE, Chung-I YANG, Yi-Feng TING, Jon-Hsu HO, Lien-Jung HUNG, Ping-Wei WANG
  • Publication number: 20240154043
    Abstract: A semiconductor device includes channel members vertically stacked, a gate structure wrapping around the channel members, a gate spacer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, and an inner spacer layer interposing the gate structure and the epitaxial feature. In a top view of the semiconductor device, the inner spacer layer has side portions in physical contact with the gate spacer and a middle portion stacked between the side portions. In a lengthwise direction of the channel members, the middle portion of the inner spacer layer is thicker than the side portions of the inner spacer layer.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 9, 2024
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240152187
    Abstract: A foldable electronic device including a first body, a second body, a hinge module, and a cover is provided. The hinge module is connected to the first body and the second body, such that the first body and the second body are rotated relatively to be folded or unfolded via the hinge module. The hinge module has a protruding rod eccentric to a rotation center of the hinge module. The cover is pivoted to the second body and located on a moving path of the protruding rod. The hinge module drives the cover to be rotated relative to the second body via the protruding rod.
    Type: Application
    Filed: October 24, 2023
    Publication date: May 9, 2024
    Applicant: Acer Incorporated
    Inventors: Chun-Hung Wen, Chun-Hsien Chen, Hui-Ping Sun, Wen-Neng Liao, Yu-Ming Lin, Kuan-Lin Chen