Patents by Inventor Lin Chen

Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12057477
    Abstract: Semiconductor structures and method for manufacturing the same are provided. The semiconductor structure includes a substrate and a first fin structure formed over the substrate. The semiconductor structure also includes an isolation structure formed around the first fin structure and a protection layer formed on the isolation structure. The semiconductor structure also includes first nanostructures formed over the first fin structure and a gate structure surrounding the first nanostructures. In addition, a bottom surface of the gate structure and the top surface of the isolation structure are separated by the protection layer.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Ting Lan, Guan-Lin Chen, Shi-Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20240258415
    Abstract: A device includes a first stack of nanostructures formed over a substrate; a second stack of nanostructures formed adjacent to the first stack; a first gate structure on the nanostructures of the first stack; a second gate structure on the nanostructures of the second stack; a first insulating wall separating the first gate structure and the second gate structure; a hard mask layer on the first gate structure and on the second gate structure; and a gate contact extending through the hard mask layer to physically and electrically contact the first gate structure.
    Type: Application
    Filed: May 3, 2023
    Publication date: August 1, 2024
    Inventors: Kuo-Cheng Chiang, Guan-Lin Chen, Jung-Chien Cheng, Shi Ning Ju, Chih-Hao Wang
  • Publication number: 20240252542
    Abstract: An exosome, a preparation method of an exosome, uses of the exosome, and a pharmaceutical composition including the exosome for treating an ischemia condition of a tissue are provided. The exosome is derived from a genetically engineered mesenchymal stem cell, and the genetically engineered mesenchymal stem cell includes an exogenous PD-L1 gene and an exogenous HGF gene.
    Type: Application
    Filed: January 29, 2024
    Publication date: August 1, 2024
    Applicant: China Medical University
    Inventors: Long-Bin Jeng, Mien-Chie Hung, Woei-Cherng Shyu, Syuan-Ling Lin, Chien-Lin Chen
  • Patent number: 12051342
    Abstract: The invention relates to a 3D pop-up card comprising a plush FIG. (3) reversibly convertible from a flat compressed state to a three-dimensional expanded state, and a foldable base (5) reversibly convertible from a flat compressed state to a three-dimensional expanded state, and a foldable card (2) having an inner side and an outer side, which is reversibly transferable from a folded closed state to an unfolded opened state, wherein the foldable base (5) is fixed to the inner side of the foldable card (2) and wherein the plush FIG. (3) is fixed to the foldable base (5), and wherein the card (2) comprises an additional support element (6) which is arranged inside the base (5) and supports the base (5) from the inside in the unfolded state of the card (2).
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: July 30, 2024
    Assignees: 100 Greetings, LLC, JAST Company Limited
    Inventors: Jen-Lin Chen, Anthony Carl Tomboc Gonzales, Jay Kamhi
  • Publication number: 20240250032
    Abstract: In an embodiment, a device includes: a lower source/drain region; an upper source/drain region; a nanostructure between the upper source/drain region and the lower source/drain region; a gate structure extending into a sidewall of the nanostructure, the gate structure including a gate dielectric and a gate electrode, an outer sidewall of the gate electrode being aligned with an outer sidewall of the gate dielectric; and a gate contact adjacent the gate structure, the gate contact extending along the outer sidewall of the gate electrode and the outer sidewall of the gate dielectric.
    Type: Application
    Filed: April 27, 2023
    Publication date: July 25, 2024
    Inventors: Kuo-Cheng Chiang, Chih-Hao Wang, Guan-Lin Chen, Yu-Xuan Huang, Jin Cai
  • Patent number: 12043638
    Abstract: A cyclic siloxane compound, composition, method, and an article including the siloxane, wherein the cyclic siloxane has the following Formula (I): wherein: each R1 and R2 is independently a (C1-C4)alkyl; each L1 and L2 is independently a single bond, an alkylene, or an alkylene bonded to a group selected from oxy, thio, carbonyl, —NH—, and combinations thereof; each R3 is independently a linear (C14-C100)alkyl; each R4 is independently a (C1-C30)alkyl, a (C2-C30)heteroalkyl having at least one oxygen, sulfur, or —NH— group, or a (C1-C30)alkyl substituted with a fluoro, thiol, isocyanato, cyanato, hydroxyl, glycidoxy, or epoxy group; with the proviso that L1, L2, and R4 are selected such that each Si atom is directly bonded to an alkylene or an alkyl; m is an integer of at least 2; n is an integer of 0 or above; m+n is an integer of at least 3; and the cyclic siloxane compound is a solid at 25° C.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: July 23, 2024
    Assignee: 3M Innovative Properties Company
    Inventors: Jitendra S. Rathore, Chetan P. Jariwala, Lin Chen
  • Patent number: 12046426
    Abstract: A key module includes a base plate, a circuit layer and a lifting mechanism. The circuit layer is disposed on the base plate. The lifting mechanism is pivotally connected with the base plate relative to the circuit layer, and the lifting mechanism has an abutment element. The abutment element could interfere with the circuit layer to reduce the noise generated by the key module during operation.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: July 23, 2024
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chun-Lin Chen, Jui-Yu Wu, Po-Hsiang Yu
  • Publication number: 20240238928
    Abstract: A grinding wheel changing structure of grinding machines includes a base to which a clamping device, a grinding device, a storage device, a gripping device are mounted thereon. The clamping device clamps workpieces. The grinding device is movable along two axes and includes a grinding wheel and a guard. The grinding wheel is located inside the guard. A lid is pivotably connected to the guard. The storage device has multiple grinding wheels detachably stored therein. The gripping device is located between the grinding device and the storage device. The gripping device is linearly movable and includes a gripping unit which is rotatable. By using the gripping device with its gripping unit to grasp the grinding wheel and shuttle back and forth, rotate between the grinding device and the storage device, to load and unload the grinding wheel.
    Type: Application
    Filed: January 11, 2024
    Publication date: July 18, 2024
    Inventors: Yong Lin CHEN, Hung Wu LEE
  • Publication number: 20240240306
    Abstract: A physical vapor deposition (PVD) system includes: a pedestal configured to accommodate a semiconductor wafer; a cover plate above the pedestal configured to hold a target; and a collimator disposed above the pedestal and below the cover plate. The collimator has an upper surface and a lower surface. The lower surface is flat, and the upper surface is non-flat. A first thickness, in a vertical direction, of the collimator at a central portion is smaller than a second thickness, in the vertical direction, of the collimator at a peripheral portion.
    Type: Application
    Filed: March 26, 2024
    Publication date: July 18, 2024
    Inventors: Kuan-Lin Chen, Tsung-Yi Chou, Wei-Der Sun, Hao-Wei Kang
  • Publication number: 20240243114
    Abstract: An electronic package structure includes first and second package modules combined with each other. The first package module includes a substrate and a first electronic component disposed thereon, at least one second electronic component, and an insulation film. The first electronic component and the second electronic component are adjacent to each other. The insulation film includes a base material and a foam glue body, and the foam glue body is viscous and compressible. The second package module includes a heat dissipation plate and a liquid metal and an insulation protrusion portion disposed thereon. The liquid metal is pressed by the heat dissipation plate and the first electronic component. The insulation protrusion portion covers and abuts against the insulation film to press the foam glue body through the base material so as to deform the foam glue body and enable the foam glue body to cover the second electronic component.
    Type: Application
    Filed: January 17, 2024
    Publication date: July 18, 2024
    Applicant: Acer Incorporated
    Inventors: Yu-Ming Lin, Mao-Neng Liao, Cheng-Wen Hsieh, Kuang-Hua Lin, Wei-Chin Chen, Kuan-Lin Chen, Chun-Chieh Wang
  • Patent number: 12041485
    Abstract: Methods, systems, and devices related to digital wireless communication, and more specifically, to techniques related to managing an integrated access backhaul (IAB) bearer for control plane signaling transmission. In one exemplary aspect, a method for wireless communication includes transmitting a first request including information controlling a backhaul bearer to a second network node. The method also includes receiving a first response from the second network node, the first response including the information controlling the backhaul bearer.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: July 16, 2024
    Assignee: ZTE Corporation
    Inventors: Mengzhen Wang, Lin Chen
  • Patent number: 12040371
    Abstract: A semiconductor structure includes a first stack of semiconductor layers disposed over a semiconductor substrate, where the first stack of semiconductor layers includes a first SiGe layer and a plurality of Si layers disposed over the first SiGe layer and the Si layers are substantially free of Ge, and a second stack of semiconductor layers disposed adjacent to the first stack of semiconductor layers, where the second stack of semiconductor layers includes the first SiGe layer and a plurality of second SiGe layers disposed over the first SiGe layer, and where the first SiGe layer and the second SiGe layers have different compositions. The semiconductor structure further includes a first metal gate stack interleaved with the first stack of semiconductor layers to form a first device and a second metal gate stack interleaved with the second stack of semiconductor layers to form a second device different from the first device.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 12038852
    Abstract: Systems, apparatus and methods are provided for using a partial logical-to-physical (L2P) address translation table for multiple namespaces to perform address translation. An exemplary embodiment may provide a method comprising: receiving a request for a first logical data address (LDA) that belongs to a first namespace (NS); searching the first NS in an entry location table (ELT) for all namespaces whose L2P entries always reside in memory; determining that the first NS is not in the ELT; searching a cache of lookup directory entries of recently accessed translation data units (TDUs) for a first TDU containing a L2P entry for the first LDA; determining that there is a cache miss; retrieving the lookup directory entry for the first TDU from an in-memory lookup directory and determining that it is not valid; reserving a TDU space for the first TDU; and generating a load request for the first TDU.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: July 16, 2024
    Assignee: Innogrit Technologies Co., Ltd.
    Inventors: Bo Fu, Lin Chen, Jie Chen, Cheng-Yun Hsu
  • Publication number: 20240228621
    Abstract: Embodiments provided herein, provide for variant IgG Fc polypeptides, dimeric molecules, pharmaceutical compositions, and methods that can be used to target at cells to modulate the activity of the same to treat disorders, such as autoimmune disorders or cancers.
    Type: Application
    Filed: October 25, 2023
    Publication date: July 11, 2024
    Inventors: Yen-Lin Chen, Ryan Peckner, Nathan Higginson-Scott, Daniela Cipolletta, Yanfeng Zhou, Kevin Lewis Otipoby, Jyothsna Visweswaraiah
  • Publication number: 20240236621
    Abstract: This disclosure relates generally to Multicast/Broadcast Service (MBS) configuration dissemination for improving network efficiency. Performed by a User Equipment (UE) in a wireless network, the method including: receiving a first message comprising a first MBS configuration associated with the MBS from a first network element of the wireless network; and receiving an MBS configuration update notification from the first network element.
    Type: Application
    Filed: April 21, 2023
    Publication date: July 11, 2024
    Applicant: ZTE Corporation
    Inventors: Tao QI, Lin CHEN, Liping WANG, Hao ZHU
  • Publication number: 20240233342
    Abstract: Introduced here is a training system that allows users to define what they would like their surveillance systems to detect, recognize, or otherwise identify. For simplicity, the use case provided by a given user for teaching purposes may be referred to as a “skill.” A surveillance system can learn each of the skills provided by its respective user from a limited number of examples. For example, the given user may only provide several examples—or even a single example—in contrast to conventional learning approaches.
    Type: Application
    Filed: May 3, 2022
    Publication date: July 11, 2024
    Inventors: Zhongwei Cheng, Vijaya Naga Jyoth Sumanth Chennupati, Lin Chen, Tianqiang Liu
  • Publication number: 20240226217
    Abstract: The present disclosure provides a method for extracting and purifying total flavonoids from Carthamus tinctorius L. leaf, and use thereof, and belongs to the technical field of extraction and use of active ingredients of traditional Chinese medicine. The method includes: heating and refluxing Carthamus tinctorius L. leaf with ethanol to obtain a mixture, where the ethanol and Carthamus tinctorius L. leaf are at a volume ratio of (20-30):1; concentrating the mixture to form a concentrated filtrate, and adsorbing the concentrated filtrate with a macroporous resin; eluting a resulting adsorbed macroporous resin with ethanol, and collecting an obtained eluate; and concentrating the eluate until there is no residual ethanol, and drying in sequence to obtain a TFFCL powder. In the present disclosure, Carthamus tinctorius L. leaf is analyzed, the TFFCL is extracted, and applications of extracted total flavonoids (TFs) are studied, thereby better utilizing the resources of Carthamus tinctorius L.
    Type: Application
    Filed: October 17, 2023
    Publication date: July 11, 2024
    Applicant: Shaanxi University of Chinese Medicine
    Inventors: Zhishu TANG, Lin CHEN, Zhongxing SONG
  • Publication number: 20240234572
    Abstract: An extended drain metal oxide semiconductor transistor includes a substrate. A gate is disposed on the substrate. A source doped region is disposed in the substrate at one side of the gate. A drain doped region is disposed in the substrate at another side of the gate. A thin gate dielectric layer is disposed under the gate. A thick gate dielectric layer is disposed under the gate. The thick gate dielectric layer extends from the bottom of the gate to contact the drain doped region. A second conductive type first well is disposed in the substrate and surrounds the source doped region and the drain doped region. A deep well is disposed within the substrate and surrounds the second conductive type first well.
    Type: Application
    Filed: February 10, 2023
    Publication date: July 11, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Liang-An Huang, Ming-Hua Tsai, Wen-Fang Lee, Chin-Chia Kuo, Jung Han, Chun-Lin Chen, Ching-Chung Yang, Nien-Chung Li
  • Patent number: 12033899
    Abstract: Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guan-Lin Chen, Chih-Hao Wang, Ching-Wei Tsai, Shi Ning Ju, Jui-Chien Huang, Kuo-Cheng Chiang, Kuan-Lun Cheng
  • Patent number: 12032499
    Abstract: A hybrid printed circuit board (PCB) topology is provided. A non-volatile storage system may include a PCB, a first non-volatile storage device attached to a first side of the PCB, a second non-volatile storage device attached to a second side of the PCB, and a storage controller coupled to the first and second non-volatile storage devices by a shared channel. The two devices may be placed in a clamshell configuration but have different capacities. The shared channel may have a first signal route to a first pin of the first non-volatile storage device and a second signal route to a second pin of the second non-volatile storage device. The first pin may have a pin capacitance that is smaller than that of the second pin. The first signal route has an extra resistor in series compared to the second signal route.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: July 9, 2024
    Assignee: InnoGrit Technologies Co., Ltd.
    Inventors: Gang Zhao, Lin Chen