Abstract: A light-guide optical element and a method for manufacturing the same, includes: a coating step including forming at least one functional coating on a surface of a substrate, and cutting the substrate to form at least one optical coating strip; a mounting step including placing at least one optical coating strip in a storage space of a first substrate; an assembling step including combining a second substrate corresponding to the first substrate with the first substrate, so that the at least one optical coating strip is positioned between the first substrate and the second substrate, forming a semi-finished product; and a cutting step including cutting the semi-finished product into at least one finished light-guide optical element, and the at least one finished light-guide optical element includes the at least one optical coating strip.

Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.

Abstract: A developer supply control device includes: an imaging component; a developer transmission channel for connecting a developer containing device and the imaging component; a developer transmission component, at least partially disposed in the developer transmission channel to transmit developer to the imaging component; a residual information feedback unit, used to send residual information of the developer in the imaging component to an image forming device, where the residual information of the developer is used to determine whether the developer needs to be supplied to the imaging component; and a state detection unit, used to detect a working state of the developer transmission component. When the image forming device acquires the working state information, the residual information of the developer and the working state information are used to determine whether to control the developer containing device to supply the developer to the developer transmission channel.

Abstract: A voice processing method includes: performing voice conversion processing based on a user voice of a target user and specified timbre information to obtain a specified converted voice having a specified timbre; training a voice conversion model based on the user voice of the target user and the specified converted voice to obtain a target voice conversion model; inputting a target text for voice synthesis and the specified timbre information into a voice synthesis model to generate an intermediate voice having the specified timbre; and performing voice conversion processing on the intermediate voice by the target voice conversion model to generate a target synthesized voice that matches a timbre of the target user.

Abstract: A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space

Abstract: A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

Abstract: A method includes forming first semiconductive sheets over a substrate and arranged in a vertical direction, and second semiconductive sheets over the substrate and arranged in the vertical direction, wherein a number of the second semiconductive sheets is different than a number of the first semiconductive sheets; forming first source/drain regions on either side of each of the first semiconductive sheets, and second source/drain regions on either side of each of the second semiconductive sheets; forming a first gate around each of the first semiconductive sheets, and a second gate around each of the second semiconductive sheets.

Abstract: A device includes first to third power/ground (PG) elements; a first set of at least three tracks between the first and second PG elements and a second set of at least three tracks between the second and third PG elements, the tracks being arranged in equal numbers between the first and second PG and second and third PG elements; a first row of cells overlapping the first set; and a second row of cells overlapping the second set. In the first row of cells, a first cell has a first height and a second cell has a greater height than the first height; in the second row of cells, a third cell has the first height and a fourth cell has a lesser height less than the first height; and a track configured as an in-cell PG track is aligned with a boundary of the second and fourth cells.

Abstract: A solid-state image sensor is provided. The solid-state image sensor includes photoelectric conversion elements and a color filter layer disposed above the photoelectric conversion elements. The color filter layer has a first color filter segment and a second color filter segment adjacent to the first color filter segment. The first color filter segment and the second color filter segment correspond to different colors. The solid-state image sensor also includes a shielding grid structure disposed between the first color filter segment and the second color filter segment. The shielding grid structure is divided into a first shielding segment and a second shielding segment. The solid-state image sensor further includes a meta structure disposed above the color filter layer. In a top view, the second shielding segment is formed as a triangle, a rectangle, or a combination thereof.

Abstract: A method for forming transistors includes forming a stack of alternating first semiconductor layers and second semiconductor layers on a substrate and forming nanostructure channels and interposers by forming a source/drain opening in a first device region of the substrate. The source/drain opening extending through the first and second semiconductor layers. The method includes, after the forming a source/drain opening, increasing tensile strain of the nanostructure channels, and, after the increasing tensile strain, forming a source/drain in the source/drain opening.

Abstract: A driving mechanism for moving an optical element is provided. The driving mechanism includes a fixed part, a movable part, and a driving assembly. The movable part is movably connected to the fixed part for holding the optical element. The driving assembly is configured for moving the movable part relative to the fixed part.

Abstract: A display device includes a display panel and a switch panel. The switch panel includes a first substrate disposed on the display panel, a shielding pattern layer, a light transmitting layer, pixel electrodes disposed on the light transmitting layer, a second substrate disposed on the pixel electrodes, and the liquid crystal layer disposed between the first substrate and the second substrate. The shielding pattern layer is disposed on the first substrate and includes opening parts and light shielding parts arranged alternately with the opening parts. Each of the light shielding parts has a first thickness. The light transmitting layer is disposed on the shielding pattern layer and includes filling parts filling the opening parts and extending parts arranged alternately with the filling parts. Each of the filling parts has a second thickness greater than the first thickness.

Abstract: A memory device including a memory array, a driver circuit, and a recover circuit is provided. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Abstract: A computer readable medium comprising computer executable instructions for carrying out a method is disclosed. The method includes: generating a schematic of an integrated circuit including a plurality of components, each of the components associated with a format, the format indicating a matching group that represents a respective circuit functionality; merging a first device array layout, which corresponds to a first subset of the components that share a first matching group, and a second device array layout, which corresponds to a second subset of the components that share a second matching group, to form a third device array layout, in response to detecting that the first device array layout and the second device array layout share a same cell type; forming a first layer enclosing the third device array layout; inserting dummy patterns surrounding the first layer; and inserting a guard ring further surrounding the dummy patterns.

Abstract: A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.

Abstract: A system having a Reconfigurable ReflectArray (RRA) structure includes a radiation layer and a control layer. The radiation layer includes at least one P-Intrinsic-N (P-I-N) diode and a plurality of reconfigurable reflective units. At least one part of the reconfigurable reflective units is electrically connected to the at least one P-I-N diode. The control layer includes at least one switch element and at least one control unit. The at least one switch element is electrically connected to the radiation layer. The at least one control unit is electrically connected to the at least one switch element. The number of the reconfigurable reflective units is different from the number of the at least one switch element.

Abstract: An anti-twist structure of a voice coil motor includes a base, a lens housing, a first elastic sheet, a second elastic sheet, a magnet, and a yoke member. The lens housing has first margin wall and a second margin wall, and a first protrusion extends from the first margin wall. The height of the second protrusion is lower than the height of the first protrusion. The yoke member has a first wall, a connection wall, a second wall, and a side wall. The first wall is disposed above the first protrusion, and the second wall is disposed above the second protrusion. The lens housing has a deflectable angle relative to a horizontal reference line. When the lens housing deflects to a maximum value of the deflectable angle, the first margin wall abuts against the second wall and/or the first protrusion abuts against the first wall.

Abstract: A bonding tool for bonding semiconductor dies to a semiconductor wafer is provided. The bonding tool includes a wafer chuck, an edge support, a hard plate, and a buffer layer. The wafer chuck carries the semiconductor wafer and the semiconductor dies placed on the semiconductor wafer. The edge support is disposed on the wafer chuck, the semiconductor wafer and the semiconductor dies are laterally surrounded by the edge support, and a top surface of the edge support substantially levels with surfaces of the semiconductor dies. The hard plate is movably disposed over the semiconductor dies, the edge support and the wafer chuck. The buffer layer is disposed on a bottom surface of the hard plate, and the buffer layer is in contact with the top surface of the edge support and the semiconductor dies when the hard plate moves towards the edge support.

Abstract: A method includes selecting one or more candidate installation positions in a bottom area below a central horizontal line of the refrigerant heat exchanger, determining one or more highest risk leakage points each corresponding to one of the one or more candidate installation positions and reflecting a refrigerant leakage position in the refrigerant heat exchanger with a lowest probability of being detected by the refrigerant sensor installed at the corresponding candidate installation position, calculating one or more leakage limit distances each corresponding to one of the one or more highest risk leakage points, determining a target highest risk leakage point corresponding to a target leakage limit distance that is a smallest one of the one or more leakage limit distances, determining a target installation position based at least on the target highest risk leakage point, and installing the refrigerant sensor at the target installation position.

Abstract: Error alert encoding for improved error mitigation is described. In one or more implementations, a system includes a processor configured to receive an encoded signal indicating a type of an error detected in a memory, and output one or more mitigation commands to mitigate the type of the error detected in the memory based on the encoded signal. In one or more implementations, a memory system includes a memory and a buffer. The buffer is configured to output an encoded signal indicating a type of an error detected in the memory.