Abstract: A package assembly and a manufacturing method thereof are provided. The package assembly includes a photonic integrated circuit component, an electric integrated circuit component, a lens and an optical signal port. The photonic integrated circuit component comprises an optical input/output portion configured to transmit and receive optical signal. The electric integrated circuit component is electrically connected to the photonic integrated circuit component. The lens is disposed on a sidewall of the photonic integrated circuit component. The optical signal port is optically coupled to the optical input/output portion.

Abstract: Provided are a silicon-based display assembly and a display device. The silicon-based display assembly is provided with a silicon-based panel, a flexible circuit board, and a logic control board. An end of the flexible circuit board is bonded to a first bonding region of the silicon-based panel. The logic control board is disposed on the flexible circuit board. The logic control board is integrated with a timing controller module, an algorithm processing module, a first input interface module, a first output interface module, and a power module. The logic control board is configured to at least perform high-speed data receiving and high-speed data processing.

Abstract: An adaptive minimum voltage aging margin prediction method includes acquiring characteristic data of a plurality of dies in a testing line, predicting a wear-out failure rate of each module of the plurality of dies according to the characteristic data by using a neural network, and predicting a minimum voltage aging margin of the each module according to the wear-out failure rate of the each module by using the neural network.

Abstract: A phase shifter includes a first substrate and a second substrate that are arranged opposite to each other and at least one phase shift unit, where the phase shift unit includes a microstrip line, an auxiliary electrode, a liquid crystal layer, and a grounding metal layer, and the auxiliary electrode is located between the first substrate and the liquid crystal layer and/or the auxiliary electrode is located between the second substrate and the liquid crystal layer.

Abstract: A solid-state image sensor is provided. The solid-state image sensor includes photoelectric conversion elements and a color filter layer disposed above the photoelectric conversion elements. The color filter layer has a first color filter segment and a second color filter segment adjacent to the first color filter segment. The first color filter segment and the second color filter segment correspond to different colors. The solid-state image sensor also includes a shielding grid structure disposed between the first color filter segment and the second color filter segment. The shielding grid structure is divided into a first shielding segment and a second shielding segment. The solid-state image sensor further includes a meta structure disposed above the color filter layer. In a top view, the second shielding segment is formed as a triangle, a rectangle, or a combination thereof.

Abstract: A method for forming transistors includes forming a stack of alternating first semiconductor layers and second semiconductor layers on a substrate and forming nanostructure channels and interposers by forming a source/drain opening in a first device region of the substrate. The source/drain opening extending through the first and second semiconductor layers. The method includes, after the forming a source/drain opening, increasing tensile strain of the nanostructure channels, and, after the increasing tensile strain, forming a source/drain in the source/drain opening.

Abstract: A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.

Abstract: An analog to digital converter for use in an electrocardiogram device is provided that includes a voltage supply; an operational amplifier, including: a positive input pin; an inverting input pin; and an output pin; an output node, connected directly to the output pin and the inverting input pin; an ECG electrode, connected to the output node via a first resistor; a reference voltage, connected directly to the output node; and a feedback node, connected to directly to the positive input pin, connected to the voltage supply via a second resistor, and connected to a ground via a third resistor and a first capacitor, wherein the third resistor and the first capacitor are connected in parallel between the feedback node and the ground.

Abstract: A voice processing method includes: performing voice conversion processing based on a user voice of a target user and specified timbre information to obtain a specified converted voice having a specified timbre; training a voice conversion model based on the user voice of the target user and the specified converted voice to obtain a target voice conversion model; inputting a target text for voice synthesis and the specified timbre information into a voice synthesis model to generate an intermediate voice having the specified timbre; and performing voice conversion processing on the intermediate voice by the target voice conversion model to generate a target synthesized voice that matches a timbre of the target user.

Abstract: A method includes forming first semiconductive sheets over a substrate and arranged in a vertical direction, and second semiconductive sheets over the substrate and arranged in the vertical direction, wherein a number of the second semiconductive sheets is different than a number of the first semiconductive sheets; forming first source/drain regions on either side of each of the first semiconductive sheets, and second source/drain regions on either side of each of the second semiconductive sheets; forming a first gate around each of the first semiconductive sheets, and a second gate around each of the second semiconductive sheets.

Abstract: A device includes first to third power/ground (PG) elements; a first set of at least three tracks between the first and second PG elements and a second set of at least three tracks between the second and third PG elements, the tracks being arranged in equal numbers between the first and second PG and second and third PG elements; a first row of cells overlapping the first set; and a second row of cells overlapping the second set. In the first row of cells, a first cell has a first height and a second cell has a greater height than the first height; in the second row of cells, a third cell has the first height and a fourth cell has a lesser height less than the first height; and a track configured as an in-cell PG track is aligned with a boundary of the second and fourth cells.

Abstract: A microwave ablation antenna assembly including a coaxial cable terminating in a radiating section, a first tubular member circumscribing the coaxial cable and spaced therefrom to permit fluid flow therebetween, and a second tubular member circumscribing the first tubular member and spaced therefrom to permit fluid flow therebetween. The microwave ablation antenna assembly further includes a hub configured to receive the coaxial cable, first tubular member, and second tubular member, the hub including a fluid inflow chamber and a fluid outflow chamber and an integrated hub divider and hub cap separating the fluid inflow chamber from the fluid outflow chamber and prohibiting fluid flow between the inflow chamber and outflow chamber except via the spacing between the coaxial cable and the first tubular member and between the first tubular member and the second tubular member.

Abstract: Systems and methods for use with a biological sample include a microscopy device, a diluent, a sample holder, and one or more of lyophilized cakes comprising artificial particles. The lyophilized cakes and the biological sample are mixed with the diluent in the sample holder to form a solution. The biological sample is imaged with the artificial particles as reference markers using the microscopy device. A settling time of the artificial particles is shorter than or equal to a settling time of the biological sample.

Abstract: A light-guide optical element and a method for manufacturing the same, includes: a coating step including forming at least one functional coating on a surface of a substrate, and cutting the substrate to form at least one optical coating strip; a mounting step including placing at least one optical coating strip in a storage space of a first substrate; an assembling step including combining a second substrate corresponding to the first substrate with the first substrate, so that the at least one optical coating strip is positioned between the first substrate and the second substrate, forming a semi-finished product; and a cutting step including cutting the semi-finished product into at least one finished light-guide optical element, and the at least one finished light-guide optical element includes the at least one optical coating strip.

Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.

Abstract: A developer supply control device includes: an imaging component; a developer transmission channel for connecting a developer containing device and the imaging component; a developer transmission component, at least partially disposed in the developer transmission channel to transmit developer to the imaging component; a residual information feedback unit, used to send residual information of the developer in the imaging component to an image forming device, where the residual information of the developer is used to determine whether the developer needs to be supplied to the imaging component; and a state detection unit, used to detect a working state of the developer transmission component. When the image forming device acquires the working state information, the residual information of the developer and the working state information are used to determine whether to control the developer containing device to supply the developer to the developer transmission channel.

Abstract: A multi-chip package comprising an interconnection substrate; a first semiconductor IC chip over the interconnection substrate, wherein the first semiconductor IC chip comprises a first silicon substrate, a plurality of first metal vias passing through the first silicon substrate, a plurality of first transistors on a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate, wherein the first interconnection scheme comprises a first interconnection metal layer over the first silicon substrate, a second interconnection metal layer over the first interconnection layer and the first silicon substrate and a first insulating dielectric layer over the first silicon substrate and between the first and second interconnection metal layers; a second semiconductor IC chip over and bonded to the first semiconductor IC chip; and a plurality of second metal vias over and coupling to the interconnection substrate, wherein the plurality of second metal vias are in a space

Abstract: A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

Abstract: A driving mechanism for moving an optical element is provided. The driving mechanism includes a fixed part, a movable part, and a driving assembly. The movable part is movably connected to the fixed part for holding the optical element. The driving assembly is configured for moving the movable part relative to the fixed part.

Abstract: A display device includes a display panel and a switch panel. The switch panel includes a first substrate disposed on the display panel, a shielding pattern layer, a light transmitting layer, pixel electrodes disposed on the light transmitting layer, a second substrate disposed on the pixel electrodes, and the liquid crystal layer disposed between the first substrate and the second substrate. The shielding pattern layer is disposed on the first substrate and includes opening parts and light shielding parts arranged alternately with the opening parts. Each of the light shielding parts has a first thickness. The light transmitting layer is disposed on the shielding pattern layer and includes filling parts filling the opening parts and extending parts arranged alternately with the filling parts. Each of the filling parts has a second thickness greater than the first thickness.