Patents by Inventor Lin Hsiao

Lin Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11959230
    Abstract: A molding system includes a frame device, a scooping device, a demolding device, a cutting device, an inspection device, a packaging device, and a conveying device. The frame device defines a scooping zone, a hot pressing zone, a cutting zone, an inspection zone, and a packaging zone. The scooping device includes a pulp tank that is adapted to contain a slurry, and a scooping mold that is adapted to scoop the slurry such that the slurry forms a blank unit thereon. The cutting device is adapted to cut the blank unit into a plurality of blank bodies. The conveying device is adapted to convey the blank bodies from the cutting zone to the packaging zone through the inspection zone.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: April 16, 2024
    Inventors: Fu-Lin Hsiao, Yang-Han Lee
  • Patent number: 11942373
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chu-An Lee, Chen-Hao Wu, Peng-Chung Jangjian, Chun-Wen Hsiao, Teng-Chun Tsai, Huang-Lin Chao
  • Publication number: 20240097888
    Abstract: In a file sharing system, a key manager unit realizes a correspondence between the first user identifier and the first public key in response to a registration request of the first user, generates a first key material for encrypting the first file into a first encrypted file, and generates a first credential according to the first user identifier, the first file identifier, the first public key and the first key material after receiving an access-right claim request to the first file from the first user. A file storage unit stores the first encrypted file and the first credential. The first user uses the first user identifier, the first file identifier and the first private key to retrieve the first key material out of the first credential, and uses the first key material to decrypt the first encrypted file into the first file.
    Type: Application
    Filed: September 18, 2023
    Publication date: March 21, 2024
    Inventors: CHIA-JUNG LIANG, CHIHHUNG LIN, CHIH-PING HSIAO, YU-JIE SU, CHIA-HSIN CHENG, TUN-HOU WANG, MENG-CHAO TSAI, YUEH-CHIN LIN
  • Patent number: 11935780
    Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: March 19, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chuan-Lin Hsiao, Wei-Ming Liao
  • Publication number: 20240047265
    Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 8, 2024
    Inventors: Chuan-Lin HSIAO, Wei-Ming LIAO
  • Patent number: 11895830
    Abstract: The present disclosure provides a method for manufacturing a semiconductor device having a buried wordline. The method includes forming a first recessed portion in a first dielectric layer in a substrate; forming a second recessed portion spaced apart from the first recessed portion and in the substrate; disposing a protection layer on the substrate to cover the second recessed portion; and disposing a second dielectric layer on the first dielectric layer.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: February 6, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chuan-Lin Hsiao
  • Patent number: 11832432
    Abstract: The present application provides a method of manufacturing a memory device having several word lines (WL) with reduced leakage. The method includes steps of providing a semiconductor substrate defined with an active area and including an isolation surrounding the active area; forming a first recess extending into the semiconductor substrate and across the active area; forming a first lining portion of a first insulating layer conformal to the first recess; disposing a first conductive material conformal to the first lining portion; forming a first conductive member surrounded by the first conductive material; disposing a second conductive material over the first conductive member to form a first conductive layer enclosing the first conductive member; and forming a first protruding portion of the first insulating layer above the first conductive layer and the first conductive member.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: November 28, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chuan-Lin Hsiao
  • Patent number: 11828023
    Abstract: A pulp transportation system is adapted for transporting a pulp among a pulp-supply machine and a plurality of forming machines, and includes a pump unit, a first pipe unit, a second pipe unit and a valve unit. The pump unit is adapted for urging the pulp to flow. The valve unit is operable to control flow of the pulp through the first pipe unit and the second pipe unit, such that the flow of the pulp is convertible between a pulp-supply state, in which the pulp flows out from the pulp supply machine into at least one of the forming machines, and a pulp-return state, in which the pulp flows out from at least one of the forming machines into the pulp supply machine.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: November 28, 2023
    Inventor: Fu-Lin Hsiao
  • Patent number: 11797442
    Abstract: An integrated circuit and a method for executing a cache management operation are provided. The integrated circuit includes a master interface, a slave interface, and a link. The link is connected between the master interface and the slave interface, and the link includes an A-channel, a B-channel, a C-channel, a D-channel, and an E-channel. The A-channel is configured to transmit a cache management operation message of the master interface to the slave interface, and the cache management operation message is configured to manage data consistency between different data caches. The D-channel is configured to transmit a cache management operation acknowledgement message of the slave interface to the master interface.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: October 24, 2023
    Assignee: ANDES TECHNOLOGY CORPORATION
    Inventors: Zhong-Ho Chen, Yu-Lin Hsiao, Hsin Ming Chen
  • Publication number: 20230262958
    Abstract: A memory structure includes a substrate, a first word line and a first word line. The substrate has a plurality of active areas and an isolation structure surrounding the active areas. The first word line trench is formed across a first active area of the active areas and the isolation structure. The first word line trench includes a first slot and a first groove. The first slot is recessed from a top surface of the substrate. The first groove expands from a bottom of the first slot. A first sidewall is connected between the bottom of the first slot and a top of the first groove. A first word line is formed in the first word line trench. The first word line comprises a gate dielectric confomally formed on the first groove and the first slot.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Inventors: Tseng-Fu LU, Chuan-Lin HSIAO
  • Patent number: 11688783
    Abstract: The present disclosure provides a semiconductor device having a buried wordline. The semiconductor device includes a substrate having a surface and a first dielectric layer extending from the surface of the substrate into the substrate. The semiconductor device also includes a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate and a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer and the second dielectric layer.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: June 27, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chuan-Lin Hsiao
  • Publication number: 20230197771
    Abstract: The present application provides a memory device having several word lines (WL) with reduced leakage and a manufacturing method of the memory device. The memory device includes a semiconductor substrate defined with an active area and including a recess extending into the semiconductor substrate; and a word line disposed within the recess, wherein the word line includes an insulating layer disposed within the recess, a conductive layer surrounded by the insulating layer, and a conductive member enclosed by the conductive layer, and the insulating layer includes a lining portion conformal to the recess and a protruding portion disposed above the conductive layer. A method of manufacturing the memory device is also disclosed.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 22, 2023
    Inventor: Chuan-Lin HSIAO
  • Publication number: 20230200044
    Abstract: The present application provides a method of manufacturing a memory device having several word lines (WL) with reduced leakage. The method includes steps of providing a semiconductor substrate defined with an active area and including an isolation surrounding the active area; forming a first recess extending into the semiconductor substrate and across the active area; forming a first lining portion of a first insulating layer conformal to the first recess; disposing a first conductive material conformal to the first lining portion; forming a first conductive member surrounded by the first conductive material; disposing a second conductive material over the first conductive member to form a first conductive layer enclosing the first conductive member; and forming a first protruding portion of the first insulating layer above the first conductive layer and the first conductive member.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 22, 2023
    Inventor: CHUAN-LIN HSIAO
  • Publication number: 20230178614
    Abstract: The present disclosure provides a semiconductor device having a buried wordline. The semiconductor device includes a substrate having a surface and a first dielectric layer extending from the surface of the substrate into the substrate. The semiconductor device also includes a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate and a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer and the second dielectric layer.
    Type: Application
    Filed: December 7, 2021
    Publication date: June 8, 2023
    Inventor: Chuan-Lin HSIAO
  • Publication number: 20230180466
    Abstract: The present disclosure provides a method for manufacturing a semiconductor device having a buried wordline. The method includes forming a first recessed portion in a first dielectric layer in a substrate; forming a second recessed portion spaced apart from the first recessed portion and in the substrate; disposing a protection layer on the substrate to cover the second recessed portion; and disposing a second dielectric layer on the first dielectric layer.
    Type: Application
    Filed: December 3, 2021
    Publication date: June 8, 2023
    Inventor: CHUAN-LIN HSIAO
  • Publication number: 20230141995
    Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.
    Type: Application
    Filed: November 11, 2021
    Publication date: May 11, 2023
    Inventors: Chuan-Lin HSIAO, Wei-Ming LIAO
  • Publication number: 20230148434
    Abstract: A pulp transportation system is adapted for transporting a pulp among a pulp-supply machine and a plurality of forming machines, and includes a pump unit, a first pipe unit, a second pipe unit and a valve unit. The pump unit is adapted for urging the pulp to flow. The valve unit is operable to control flow of the pulp through the first pipe unit and the second pipe unit, such that the flow of the pulp is convertible between a pulp-supply state, in which the pulp flows out from the pulp supply machine into at least one of the forming machines, and a pulp-return state, in which the pulp flows out from at least one of the forming machines into the pulp supply machine.
    Type: Application
    Filed: August 23, 2022
    Publication date: May 11, 2023
    Inventor: Fu-Lin HSIAO
  • Publication number: 20230122423
    Abstract: An integrated circuit and a method for executing a cache management operation are provided. The integrated circuit includes a master interface, a slave interface, and a link. The link is connected between the master interface and the slave interface, and the link includes an A-channel, a B-channel, a C-channel, a D-channel, and an E-channel. The A-channel is configured to transmit a cache management operation message of the master interface to the slave interface, and the cache management operation message is configured to manage data consistency between different data caches. The D-channel is configured to transmit a cache management operation acknowledgement message of the slave interface to the master interface.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 20, 2023
    Applicant: ANDES TECHNOLOGY CORPORATION
    Inventors: Zhong-Ho Chen, Yu-Lin Hsiao, Hsin Ming Chen
  • Publication number: 20220275586
    Abstract: A molding system includes a frame device, a scooping device, a demolding device, a cutting device, an inspection device, a packaging device, and a conveying device. The frame device defines a scooping zone, a hot pressing zone, a cutting zone, an inspection zone, and a packaging zone. The scooping device includes a pulp tank that is adapted to contain a slurry, and a scooping mold that is adapted to scoop the slurry such that the slurry forms a blank unit thereon. The cutting device is adapted to cut the blank unit into a plurality of blank bodies. The conveying device is adapted to convey the blank bodies from the cutting zone to the packaging zone through the inspection zone.
    Type: Application
    Filed: February 24, 2022
    Publication date: September 1, 2022
    Inventors: Fu-Lin HSIAO, Yang-Han LEE
  • Patent number: D956436
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: July 5, 2022
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Ying Hua Yang, Pei-Chun Chang, Chao Ren, I Lin Hsiao